From: Andi Kleen <ak@suse.de>
To: Zwane Mwaikambo <zwane@linuxpower.ca>
Cc: Linux Kernel <linux-kernel@vger.kernel.org>, Dave Jones <davej@suse.de>
Subject: Re: [PATCH][2.5][RFT] sfence wmb for K7,P3,VIAC3-2(?)
Date: 01 Apr 2003 12:11:00 +0200 [thread overview]
Message-ID: <1049191863.30759.3.camel@averell> (raw)
In-Reply-To: <Pine.LNX.4.50.0304010320220.8773-100000@montezuma.mastecende.com>
On Tue, 2003-04-01 at 10:22, Zwane Mwaikambo wrote:
> On Tue, 1 Apr 2003, Zwane Mwaikambo wrote:
>
> > +config X86_SSE
> > + bool
> > + depends on MK7 || MPENTIUMIII || MVIAC3_2
> > + default y
> > +
>
> Bad option to flag against as pointed out by someone, seeing as K7
> implimented half the SSE instructions.
SSE2 != SSE1. K7 has SSE1, like the Pentium 3.
X86_SSE is SSE1
sfence is part of SSE2. That's X86_SSE2
-Andi
next prev parent reply other threads:[~2003-04-01 9:59 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-04-01 8:05 [PATCH][2.5][RFT] sfence wmb for K7,P3,VIAC3-2(?) Zwane Mwaikambo
2003-04-01 8:22 ` Zwane Mwaikambo
2003-04-01 10:11 ` Andi Kleen [this message]
2003-04-01 11:28 ` Dave Jones
2003-04-01 11:49 ` Andi Kleen
2003-04-01 16:07 ` Zwane Mwaikambo
2003-04-01 16:26 ` Dave Jones
2003-04-01 18:31 ` Daniel Egger
2003-04-01 23:32 ` Dave Jones
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