Re: [RFC] Relaxed PIO read vs. DMA write ordering

[James Bottomley <James.Bottomley@steeleye.com>]

On Thu, 2004-01-08 at 13:44, Grant Grundler wrote:
> I haven't studied "part II" closely enough to figure out if adding
> pci_sync_consistent() would outright replace much of the DMA-API
> interface. The main issue is cacheline ownership.
> 
> pci_sync_consistent() needs to indicate CPU wants ownership of outstanding
> cachelines vs IO device wanting to own them.
> SN2 doesn't care about the latter case since it's "mostly coherent".
> SN2 just needs to flush in-flight DMA and it's coherent again.
> But older non-coherent platforms do care.
> 
> I trust James understands this better than I given the fun
> he's had with old parisc HW (715/50).

Sorry for being a bit late...I was travelling and didn't have the time
to go over the whole thread until now.

Let me clarify what Part II of the DMA-API is about: it's for drivers
who may be required to operate both on hardware that has a coherency
domain and hardware that hasn't.

Its design is primarily to be as efficient as possible on coherency
domain hardware.

I think it can do exactly what you want for the RO case, because it was
tailored for almost precisely this problem (guaranteeing mailbox
reads/writes become coherent).  I think dma_cache_sync() corresponds
almost exactly to the semantics you would require of
pci_sync_coherent().

Of course, it's not the whole solution because even on hardware without
a coherency domain, PIO reads/writes are still coherent.

James