From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: Chris Friesen <cfriesen@nortelnetworks.com>
Cc: Linux Kernel list <linux-kernel@vger.kernel.org>,
Tom Rini <trini@kernel.crashing.org>
Subject: Re: problem with cache flush routine for G5?
Date: Fri, 05 Mar 2004 10:51:08 +1100 [thread overview]
Message-ID: <1078444268.5698.27.camel@gaston> (raw)
In-Reply-To: <40479A50.9090605@nortelnetworks.com>
On Fri, 2004-03-05 at 08:06, Chris Friesen wrote:
> We're running into issues with the "flush_data_cache" routine on the G5.
>
> For the G5, the L1 dcache is 32K and the L2 cache is 512K. At 128
> bytes/cacheline, that's 256 and 4096 cachelines, respectively.
>
> In the existing tree, NUM_CACHE_LINES is set to 128*8, or 1024. Is this
> an oversight or am I missing something?
>
> Also, I'm curious why the dcbf instruction is not used for this.
First of all, why do you need to flush the cache at all ?
If you are talking about the cache flush in the 32 bits bootloaders,
then yes, this seem to be broken, you should ask Tom Rini who
maintain these things.
The kernel proper definitely doesn't contain such a routine.
Ben.
next prev parent reply other threads:[~2004-03-04 23:51 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-03-04 21:06 problem with cache flush routine for G5? Chris Friesen
2004-03-04 23:51 ` Benjamin Herrenschmidt [this message]
2004-03-04 23:57 ` Tom Rini
2004-03-05 0:04 ` Benjamin Herrenschmidt
2004-03-05 0:44 ` Chris Friesen
2004-03-05 15:15 ` Tom Rini
2004-03-05 23:51 ` Benjamin Herrenschmidt
2004-03-05 0:37 ` Chris Friesen
2004-03-05 2:10 ` Benjamin Herrenschmidt
2004-03-05 5:39 ` Chris Friesen
2004-03-05 5:46 ` Benjamin Herrenschmidt
2004-03-05 17:21 ` Chris Friesen
2004-03-05 23:53 ` Benjamin Herrenschmidt
2004-03-06 1:34 ` Segher Boessenkool
2004-03-06 2:31 ` Anton Blanchard
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