Re: [PATCH] Configure IDE probe delays

[Lee Revell <rlrevell@joe-job.com>]

On Wed, 2004-09-01 at 11:36, Mark Lord wrote:
> With good ADMA or host-queuing controllers that access system
> memory directly for their command blocks, then there's not much
> (if any) penalty for the extra LBA48 setup.  But for "normal"
> controllers (if such a beast even exists), the extra writes across
> the PCI bus can be costly.
> 
> Hardware write-buffer FIFOs between the CPU and the PCI bus
> can reduce the impact of this somewhat, but they are often
> only 2-4 entries deep, and will be filled by a normal (S)ATA
> command setup sequence.
> 
> This is one of those finer points that is very difficult to measure,
> since the I/O throughput is pretty much unaffected by it.  But CPU
> cycle count per-I/O setup is one way to measure it.
> 

The effect can be measured using a recent version of the voluntary
preemption patches, and disabling hardirq preemption.  In this situation
the IDE I/O completion is by far the longest non-preemptible code path,
so can be easily profiled from the latency traces.

Lee