Re: Fwd: Re: flush_cache_page()

[James Bottomley <James.Bottomley@SteelEye.com>]

On Sat, 2005-01-29 at 11:37 +0000, Russell King wrote:
> Thanks for the response.  However, apart from Ralph, Paul and yourself,
> it seems none of the other architecture maintainers care about this
> patch - the original mail was BCC'd to the architecture list.  Maybe
> that's an implicit acceptance of this patch, I don't know.

Well, OK, I'll try to answer for parisc, since we have huge VIPT
aliasing caches as well.

Right now, we have a scheme in flush_cache_page to make sure it's only
called when necessary (cache flushes are expensive for us and show up as
the primary cpu consumer in all of our profiles).  Our scheme is to see
if a translation exists for the page and skip the flush if it doesn't.

Obviously, like MIPS, we're also walking the page tables without
locking...

Looking at the callers of this, it seems it would be very unlikely to
call this with a missing translation, in that case, we can use the pfn
to flush the page through a temporary alias space instead and just take
the odd hit if no translation exists.  

> In other words, unless I actually receive some real help from the other
> architecture maintainers on this to address your concerns, ARM version 6
> CPUs with aliasing L1 caches (== >16K) will remain a dead dodo with
> mainline Linux kernels.

I've probably been told and forgotten, but what problems do you have
with your VIPT (Arm 6 is VIPT, not VIVT, right?) cache >16k which we
don't have with our 4MB VIPT caches on pa (which work, but cause us
grief with enormous amounts of flushing)?

James