* PCI bug in 2.6.13
@ 2005-09-09 16:04 Miguel
2005-09-10 5:59 ` Andrew Morton
0 siblings, 1 reply; 15+ messages in thread
From: Miguel @ 2005-09-09 16:04 UTC (permalink / raw)
To: linux-kernel
After switching from 2.6.13-rc7 to 2.6.13 I've started to have corrupted
data written on my hard disks, there was appearing blocks of 0x00 bytes
in between the data. I've tracked when this started to happen in the git
patches and I've found that this bug is due to the changes done in the
file drivers/pci/setup-res.c of 2.6.13-rc7-git2 patch. Now I run a 2.6.13
kernel with that file unmodified and everything is ok.
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: PCI bug in 2.6.13
2005-09-09 16:04 PCI bug in 2.6.13 Miguel
@ 2005-09-10 5:59 ` Andrew Morton
2005-09-10 9:36 ` Miguel
0 siblings, 1 reply; 15+ messages in thread
From: Andrew Morton @ 2005-09-10 5:59 UTC (permalink / raw)
To: Miguel; +Cc: linux-kernel, Linus Torvalds
Miguel <frankpoole@terra.es> wrote:
>
> After switching from 2.6.13-rc7 to 2.6.13 I've started to have corrupted
> data written on my hard disks, there was appearing blocks of 0x00 bytes
> in between the data. I've tracked when this started to happen in the git
> patches and I've found that this bug is due to the changes done in the
> file drivers/pci/setup-res.c of 2.6.13-rc7-git2 patch. Now I run a 2.6.13
> kernel with that file unmodified and everything is ok.
Ugly. I assume you're referring to this?
http://www.kernel.org/git/gitweb.cgi?p=linux/kernel/git/torvalds/linux-2.6.git;a=blobdiff;h=50d6685dcbcce801682c9600a81be2a98f90f8a1;hp=5598b4714f77ac2efaf0f545e404b4c9163c4fcf;hb=755528c860b05fcecda1c88a2bdaffcb50760a7f;f=drivers/pci/setup-res.c
Ignore disabled ROM resources at setup
Writing even a disabled value seems to mess up some matrox graphics
cards. It may be a card-related issue, but we may also be writing
reserved low bits in the result.
This was a fall-out of switching x86 over to the generic PCI resource
allocation code, and needs more debugging. In particular, the old x86
code defaulted to not doing any resource allocations at all for ROM
resources.
In the meantime, this has been reported to make X happier by Helge
Hafting <helgehaf@aitel.hist.no>.
diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c
--- a/drivers/pci/setup-res.c
+++ b/drivers/pci/setup-res.c
@@ -53,7 +53,9 @@ pci_update_resource(struct pci_dev *dev,
if (resno < 6) {
reg = PCI_BASE_ADDRESS_0 + 4 * resno;
} else if (resno == PCI_ROM_RESOURCE) {
- new |= res->flags & IORESOURCE_ROM_ENABLE;
+ if (!(res->flags & IORESOURCE_ROM_ENABLE))
+ return;
+ new |= PCI_ROM_ADDRESS_ENABLE;
reg = dev->rom_base_reg;
} else {
/* Hmm, non-standard resource. */
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: PCI bug in 2.6.13
2005-09-10 5:59 ` Andrew Morton
@ 2005-09-10 9:36 ` Miguel
2005-09-10 16:51 ` Linus Torvalds
0 siblings, 1 reply; 15+ messages in thread
From: Miguel @ 2005-09-10 9:36 UTC (permalink / raw)
To: Andrew Morton; +Cc: linux-kernel, torvalds
Andrew:
> Miguel <frankpoole@terra.es> wrote:
> >
> > After switching from 2.6.13-rc7 to 2.6.13 I've started to have corrupted
> > data written on my hard disks, there was appearing blocks of 0x00 bytes
> > in between the data. I've tracked when this started to happen in the git
> > patches and I've found that this bug is due to the changes done in the
> > file drivers/pci/setup-res.c of 2.6.13-rc7-git2 patch. Now I run a 2.6.13
> > kernel with that file unmodified and everything is ok.
>
> Ugly. I assume you're referring to this?
>
> http://www.kernel.org/git/gitweb.cgi?p=linux/kernel/git/torvalds/linux-2.6.git;a=blobdiff;h=50d6685dcbcce801682c9600a81be2a98f90f8a1;hp=5598b4714f77ac2efaf0f545e404b4c9163c4fcf;hb=755528c860b05fcecda1c88a2bdaffcb50760a7f;f=drivers/pci/setup-res.c
>
>
> Ignore disabled ROM resources at setup
>
> Writing even a disabled value seems to mess up some matrox graphics
> cards. It may be a card-related issue, but we may also be writing
> reserved low bits in the result.
>
> This was a fall-out of switching x86 over to the generic PCI resource
> allocation code, and needs more debugging. In particular, the old x86
> code defaulted to not doing any resource allocations at all for ROM
> resources.
>
> In the meantime, this has been reported to make X happier by Helge
> Hafting <helgehaf@aitel.hist.no>.
>
>
> diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c
> --- a/drivers/pci/setup-res.c
> +++ b/drivers/pci/setup-res.c
> @@ -53,7 +53,9 @@ pci_update_resource(struct pci_dev *dev,
> if (resno < 6) {
> reg = PCI_BASE_ADDRESS_0 + 4 * resno;
> } else if (resno == PCI_ROM_RESOURCE) {
> - new |= res->flags & IORESOURCE_ROM_ENABLE;
> + if (!(res->flags & IORESOURCE_ROM_ENABLE))
> + return;
> + new |= PCI_ROM_ADDRESS_ENABLE;
> reg = dev->rom_base_reg;
> } else {
> /* Hmm, non-standard resource. */
>
>
Yes, that is.
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: PCI bug in 2.6.13
2005-09-10 9:36 ` Miguel
@ 2005-09-10 16:51 ` Linus Torvalds
2005-09-10 21:06 ` Linus Torvalds
0 siblings, 1 reply; 15+ messages in thread
From: Linus Torvalds @ 2005-09-10 16:51 UTC (permalink / raw)
To: Miguel; +Cc: Andrew Morton, linux-kernel
On Sat, 10 Sep 2005, Miguel wrote:
>
> > Ugly. I assume you're referring to this?
> >
> > Ignore disabled ROM resources at setup
>
> Yes, that is.
Can you show the differences in "/sbin/lspci -vvx" with and without that
patch? It really makes no sense for so many reasons that it's not even
funny.
Also, what disk controller is this happening on?
Linus
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: PCI bug in 2.6.13
2005-09-10 16:51 ` Linus Torvalds
@ 2005-09-10 21:06 ` Linus Torvalds
2005-09-11 1:08 ` Miguel
0 siblings, 1 reply; 15+ messages in thread
From: Linus Torvalds @ 2005-09-10 21:06 UTC (permalink / raw)
To: Miguel; +Cc: Andrew Morton, linux-kernel
On Sat, 10 Sep 2005, Linus Torvalds wrote:
>
> Can you show the differences in "/sbin/lspci -vvx" with and without that
> patch? It really makes no sense for so many reasons that it's not even
> funny.
>
> Also, what disk controller is this happening on?
Oh, one more thing: the pci_map_rom() bug might have mapped some ROM image
in your system at a bogus address, and that might cause problems.
Now, not many drivers use pci_map_rom(), and for video ROMs this bug
should be hidden by the fact that video ROMs end up using the shadow
system rom on x86, but it's possible that you had something that used the
sysfs rom code to enable a ROM and that causes problems.
If so, the bug should be fixed in the 2.6.13.1 -stable release and/or in
the current -git snapshots, so it would be very nice if you could test one
of those..
Linus
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: PCI bug in 2.6.13
2005-09-10 21:06 ` Linus Torvalds
@ 2005-09-11 1:08 ` Miguel
2005-09-11 1:41 ` Linus Torvalds
0 siblings, 1 reply; 15+ messages in thread
From: Miguel @ 2005-09-11 1:08 UTC (permalink / raw)
To: Linus Torvalds; +Cc: akpm, linux-kernel
Linus:
> > Can you show the differences in "/sbin/lspci -vvx" with and without that
> > patch? It really makes no sense for so many reasons that it's not even
> > funny.
Below are the output of each lspci, the patched (non working) and the unpatched (working ok).
> > Also, what disk controller is this happening on?
I'm not sure because I have a software RAID0 of 3x20GB, two hard disks are in the VIA controller and the other is in the onboard HPT370 controller. Doing a diff between the lspci outputs there are some bytes different in the data of the HPT370 controller, maybe there is the problem.
> If so, the bug should be fixed in the 2.6.13.1 -stable release and/or in
> the current -git snapshots, so it would be very nice if you could test one
> of those..
I have tested both (.1 and git10) and the problem is still there.
-----lspci-patched.log-----
00:00.0 Host bridge: VIA Technologies, Inc. VT82C693A/694x [Apollo PRO133x] (rev c4)
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR-
Latency: 8
Region 0: Memory at e0000000 (32-bit, prefetchable) [size=128M]
Capabilities: [a0] AGP version 2.0
Status: RQ=32 Iso- ArqSz=0 Cal=0 SBA+ ITACoh- GART64- HTrans- 64bit- FW- AGP3- Rate=x1,x2,x4
Command: RQ=1 ArqSz=0 Cal=0 SBA- AGP- GART64- 64bit- FW- Rate=<none>
Capabilities: [c0] Power Management version 2
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 06 11 91 06 06 00 10 22 c4 00 00 06 00 08 00 00
10: 08 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00
00:01.0 PCI bridge: VIA Technologies, Inc. VT82C598/694x [Apollo MVP3/Pro133x AGP] (prog-if 00 [Normal decode])
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR-
Latency: 0
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
I/O behind bridge: 0000a000-0000afff
Memory behind bridge: e8000000-e9ffffff
Prefetchable memory behind bridge: c0000000-dfffffff
BridgeCtl: Parity- SERR- NoISA+ VGA+ MAbort- >Reset- FastB2B-
Capabilities: [80] Power Management version 2
Flags: PMEClk- DSI- D1+ D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 06 11 98 85 07 00 30 22 00 00 04 06 00 00 01 00
10: 00 00 00 00 00 00 00 00 00 01 01 00 a0 a0 00 00
20: 00 e8 f0 e9 00 c0 f0 df 00 00 00 00 00 00 00 00
30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 0c 00
00:07.0 ISA bridge: VIA Technologies, Inc. VT82C596 ISA [Mobile South] (rev 23)
Subsystem: VIA Technologies, Inc. VT82C596/A/B PCI to ISA Bridge
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B-
Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 0
00: 06 11 96 05 87 00 00 02 23 00 01 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00:07.1 IDE interface: VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE (rev 10) (prog-if 8a [Master SecP PriP])
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 32
Region 4: I/O ports at cc00 [size=16]
Capabilities: [c0] Power Management version 2
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 06 11 71 05 07 00 90 02 10 8a 01 01 00 20 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 cc 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 c0 00 00 00 00 00 00 00 ff 00 00 00
00:07.2 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller (rev 11) (prog-if 00 [UHCI])
Subsystem: VIA Technologies, Inc. (Wrong ID) USB Controller
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 32, cache line size 08
Interrupt: pin D routed to IRQ 5
Region 4: I/O ports at c000 [size=32]
Capabilities: [80] Power Management version 2
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 06 11 38 30 07 00 10 02 11 00 03 0c 08 20 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 c0 00 00 00 00 00 00 00 00 00 00 25 09 34 12
30: 00 00 00 00 80 00 00 00 00 00 00 00 05 04 00 00
00:07.3 Bridge: VIA Technologies, Inc. VT82C596 Power Management (rev 30)
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
00: 06 11 50 30 00 00 80 02 30 00 80 06 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00:08.0 Multimedia video controller: Brooktree Corporation Bt848 Video Capture (rev 12)
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 32 (4000ns min, 10000ns max)
Interrupt: pin A routed to IRQ 11
Region 0: Memory at eb105000 (32-bit, prefetchable) [size=4K]
00: 9e 10 50 03 06 00 80 02 12 00 00 04 00 20 00 00
10: 08 50 10 eb 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 10 28
00:09.0 Multimedia audio controller: Creative Labs SB Audigy (rev 04)
Subsystem: Creative Labs SB0240 Audigy 2 Platinum 6.1
Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 32 (500ns min, 5000ns max)
Interrupt: pin A routed to IRQ 10
Region 0: I/O ports at c400 [size=64]
Capabilities: [dc] Power Management version 2
Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 02 11 04 00 05 00 90 02 04 00 01 04 00 20 80 00
10: 01 c4 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 02 11 07 10
30: 00 00 00 00 dc 00 00 00 00 00 00 00 0a 01 02 14
00:09.1 Input device controller: Creative Labs SB Audigy MIDI/Game port (rev 04)
Subsystem: Creative Labs SB Audigy MIDI/Game Port
Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 32
Region 0: I/O ports at c800 [size=8]
Capabilities: [dc] Power Management version 2
Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 02 11 03 70 05 00 90 02 04 00 80 09 00 20 80 00
10: 01 c8 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 02 11 40 00
30: 00 00 00 00 dc 00 00 00 00 00 00 00 00 00 00 00
00:09.2 FireWire (IEEE 1394): Creative Labs SB Audigy FireWire Port (rev 04) (prog-if 10 [OHCI])
Subsystem: Creative Labs SB Audigy FireWire Port
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 32 (500ns min, 1000ns max), cache line size 08
Interrupt: pin B routed to IRQ 9
Region 0: Memory at eb104000 (32-bit, non-prefetchable) [size=2K]
Region 1: Memory at eb100000 (32-bit, non-prefetchable) [size=16K]
Capabilities: [44] Power Management version 2
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 02 11 01 40 06 00 10 02 04 10 00 0c 08 20 80 00
10: 00 40 10 eb 00 00 10 eb 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 02 11 10 00
30: 00 00 00 00 44 00 00 00 00 00 00 00 09 02 02 04
00:0a.0 PCI bridge: Digital Equipment Corporation DECchip 21152 (rev 03) (prog-if 00 [Normal decode])
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-
Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 32, cache line size 08
Bus: primary=00, secondary=02, subordinate=02, sec-latency=32
I/O behind bridge: 0000b000-0000bfff
Memory behind bridge: eb000000-eb0fffff
BridgeCtl: Parity- SERR+ NoISA+ VGA- MAbort- >Reset- FastB2B-
Capabilities: [dc] Power Management version 1
Flags: PMEClk- DSI- D1- D2- AuxCurrent=220mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Bridge: PM- B3+
00: 11 10 24 00 07 01 90 02 03 00 04 06 08 20 01 00
10: 00 00 00 00 00 00 00 00 00 02 02 20 b1 b1 80 02
20: 00 eb 00 eb f1 ff 01 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 dc 00 00 00 00 00 00 00 00 00 06 00
00:0b.0 Mass storage controller: Triones Technologies, Inc. HPT366/368/370/370A/372/372N (rev 04)
Subsystem: Triones Technologies, Inc. HPT370A
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 120 (2000ns min, 2000ns max), cache line size 08
Interrupt: pin A routed to IRQ 11
Region 0: I/O ports at d000 [size=8]
Region 1: I/O ports at d400 [size=4]
Region 2: I/O ports at d800 [size=8]
Region 3: I/O ports at dc00 [size=4]
Region 4: I/O ports at e000 [size=256]
Expansion ROM at 40000000 [disabled] [size=128K]
Capabilities: [60] Power Management version 2
Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 03 11 04 00 07 00 30 02 04 00 80 01 08 78 00 00
10: 01 d0 00 00 01 d4 00 00 01 d8 00 00 01 dc 00 00
20: 01 e0 00 00 00 00 00 00 00 00 00 00 03 11 01 00
30: 01 00 00 00 60 00 00 00 00 00 00 00 0b 01 08 08
01:00.0 VGA compatible controller: ATI Technologies Inc RV350 AP [Radeon 9600] (prog-if 00 [VGA])
Subsystem: PC Partner Limited: Unknown device 0200
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 32 (2000ns min), cache line size 08
Interrupt: pin A routed to IRQ 11
Region 0: Memory at c0000000 (32-bit, prefetchable) [size=256M]
Region 1: I/O ports at a000 [size=256]
Region 2: Memory at e9000000 (32-bit, non-prefetchable) [size=64K]
Expansion ROM at e8000000 [disabled] [size=128K]
Capabilities: [58] AGP version 2.0
Status: RQ=80 Iso- ArqSz=0 Cal=0 SBA+ ITACoh- GART64- HTrans- 64bit- FW+ AGP3- Rate=x1,x2,x4
Command: RQ=1 ArqSz=0 Cal=0 SBA+ AGP- GART64- 64bit- FW- Rate=<none>
Capabilities: [50] Power Management version 2
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 02 10 50 41 07 00 b0 02 00 00 00 03 08 20 80 00
10: 08 00 00 c0 01 a0 00 00 00 00 00 e9 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 4b 17 00 02
30: 00 00 00 00 58 00 00 00 00 00 00 00 0b 01 08 00
01:00.1 Display controller: ATI Technologies Inc RV350 AP [Radeon 9600] (Secondary)
Subsystem: PC Partner Limited: Unknown device 0201
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 32 (2000ns min), cache line size 08
Region 0: Memory at d0000000 (32-bit, prefetchable) [size=256M]
Region 1: Memory at e9010000 (32-bit, non-prefetchable) [size=64K]
Capabilities: [50] Power Management version 2
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 02 10 70 41 07 00 b0 02 00 00 80 03 08 20 00 00
10: 08 00 00 d0 00 00 01 e9 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 4b 17 01 02
30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 08 00
02:04.0 Ethernet controller: Intel Corporation 8255xER/82551IT Fast Ethernet Controller (rev 09)
Subsystem: Matrox Graphics, Inc.: Unknown device 6000
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 32 (2000ns min, 14000ns max), cache line size 08
Interrupt: pin A routed to IRQ 10
Region 0: Memory at eb083000 (32-bit, non-prefetchable) [size=4K]
Region 1: I/O ports at b000 [size=64]
Region 2: Memory at eb000000 (32-bit, non-prefetchable) [size=128K]
Capabilities: [dc] Power Management version 2
Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=2 PME-
00: 86 80 09 12 07 00 90 02 09 00 00 02 08 20 00 00
10: 00 30 08 eb 01 b0 00 00 00 00 00 eb 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 2b 10 00 60
30: 00 00 00 00 dc 00 00 00 00 00 00 00 09 01 08 38
02:05.0 Ethernet controller: Intel Corporation 8255xER/82551IT Fast Ethernet Controller (rev 09)
Subsystem: Matrox Graphics, Inc.: Unknown device 6000
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 32 (2000ns min, 14000ns max), cache line size 08
Interrupt: pin A routed to IRQ 5
Region 0: Memory at eb081000 (32-bit, non-prefetchable) [size=4K]
Region 1: I/O ports at b400 [size=64]
Region 2: Memory at eb020000 (32-bit, non-prefetchable) [size=128K]
Capabilities: [dc] Power Management version 2
Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=2 PME-
00: 86 80 09 12 07 00 90 02 09 00 00 02 08 20 00 00
10: 00 10 08 eb 01 b4 00 00 00 00 02 eb 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 2b 10 00 60
30: 00 00 00 00 dc 00 00 00 00 00 00 00 05 01 08 38
02:06.0 Ethernet controller: Intel Corporation 8255xER/82551IT Fast Ethernet Controller (rev 09)
Subsystem: Matrox Graphics, Inc.: Unknown device 6000
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 32 (2000ns min, 14000ns max), cache line size 08
Interrupt: pin A routed to IRQ 11
Region 0: Memory at eb080000 (32-bit, non-prefetchable) [size=4K]
Region 1: I/O ports at b800 [size=64]
Region 2: Memory at eb040000 (32-bit, non-prefetchable) [size=128K]
Capabilities: [dc] Power Management version 2
Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=2 PME-
00: 86 80 09 12 07 00 90 02 09 00 00 02 08 20 00 00
10: 00 00 08 eb 01 b8 00 00 00 00 04 eb 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 2b 10 00 60
30: 00 00 00 00 dc 00 00 00 00 00 00 00 0b 01 08 38
02:07.0 Ethernet controller: Intel Corporation 8255xER/82551IT Fast Ethernet Controller (rev 09)
Subsystem: Matrox Graphics, Inc.: Unknown device 6000
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 32 (2000ns min, 14000ns max), cache line size 08
Interrupt: pin A routed to IRQ 10
Region 0: Memory at eb082000 (32-bit, non-prefetchable) [size=4K]
Region 1: I/O ports at bc00 [size=64]
Region 2: Memory at eb060000 (32-bit, non-prefetchable) [size=128K]
Capabilities: [dc] Power Management version 2
Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=2 PME-
00: 86 80 09 12 07 00 90 02 09 00 00 02 08 20 00 00
10: 00 20 08 eb 01 bc 00 00 00 00 06 eb 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 2b 10 00 60
30: 00 00 00 00 dc 00 00 00 00 00 00 00 0a 01 08 38
-----lspci-unpatched.log-----
00:00.0 Host bridge: VIA Technologies, Inc. VT82C693A/694x [Apollo PRO133x] (rev c4)
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR-
Latency: 8
Region 0: Memory at e0000000 (32-bit, prefetchable) [size=128M]
Capabilities: [a0] AGP version 2.0
Status: RQ=32 Iso- ArqSz=0 Cal=0 SBA+ ITACoh- GART64- HTrans- 64bit- FW- AGP3- Rate=x1,x2,x4
Command: RQ=1 ArqSz=0 Cal=0 SBA- AGP- GART64- 64bit- FW- Rate=<none>
Capabilities: [c0] Power Management version 2
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 06 11 91 06 06 00 10 22 c4 00 00 06 00 08 00 00
10: 08 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00
00:01.0 PCI bridge: VIA Technologies, Inc. VT82C598/694x [Apollo MVP3/Pro133x AGP] (prog-if 00 [Normal decode])
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR-
Latency: 0
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
I/O behind bridge: 0000a000-0000afff
Memory behind bridge: e8000000-e9ffffff
Prefetchable memory behind bridge: c0000000-dfffffff
BridgeCtl: Parity- SERR- NoISA+ VGA+ MAbort- >Reset- FastB2B-
Capabilities: [80] Power Management version 2
Flags: PMEClk- DSI- D1+ D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 06 11 98 85 07 00 30 22 00 00 04 06 00 00 01 00
10: 00 00 00 00 00 00 00 00 00 01 01 00 a0 a0 00 00
20: 00 e8 f0 e9 00 c0 f0 df 00 00 00 00 00 00 00 00
30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 0c 00
00:07.0 ISA bridge: VIA Technologies, Inc. VT82C596 ISA [Mobile South] (rev 23)
Subsystem: VIA Technologies, Inc. VT82C596/A/B PCI to ISA Bridge
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B-
Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 0
00: 06 11 96 05 87 00 00 02 23 00 01 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00:07.1 IDE interface: VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE (rev 10) (prog-if 8a [Master SecP PriP])
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 32
Region 4: I/O ports at cc00 [size=16]
Capabilities: [c0] Power Management version 2
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 06 11 71 05 07 00 90 02 10 8a 01 01 00 20 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 cc 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 c0 00 00 00 00 00 00 00 ff 00 00 00
00:07.2 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller (rev 11) (prog-if 00 [UHCI])
Subsystem: VIA Technologies, Inc. (Wrong ID) USB Controller
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 32, cache line size 08
Interrupt: pin D routed to IRQ 5
Region 4: I/O ports at c000 [size=32]
Capabilities: [80] Power Management version 2
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 06 11 38 30 07 00 10 02 11 00 03 0c 08 20 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 c0 00 00 00 00 00 00 00 00 00 00 25 09 34 12
30: 00 00 00 00 80 00 00 00 00 00 00 00 05 04 00 00
00:07.3 Bridge: VIA Technologies, Inc. VT82C596 Power Management (rev 30)
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
00: 06 11 50 30 00 00 80 02 30 00 80 06 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00:08.0 Multimedia video controller: Brooktree Corporation Bt848 Video Capture (rev 12)
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 32 (4000ns min, 10000ns max)
Interrupt: pin A routed to IRQ 11
Region 0: Memory at eb105000 (32-bit, prefetchable) [size=4K]
00: 9e 10 50 03 06 00 80 02 12 00 00 04 00 20 00 00
10: 08 50 10 eb 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 10 28
00:09.0 Multimedia audio controller: Creative Labs SB Audigy (rev 04)
Subsystem: Creative Labs SB0240 Audigy 2 Platinum 6.1
Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 32 (500ns min, 5000ns max)
Interrupt: pin A routed to IRQ 10
Region 0: I/O ports at c400 [size=64]
Capabilities: [dc] Power Management version 2
Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 02 11 04 00 05 00 90 02 04 00 01 04 00 20 80 00
10: 01 c4 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 02 11 07 10
30: 00 00 00 00 dc 00 00 00 00 00 00 00 0a 01 02 14
00:09.1 Input device controller: Creative Labs SB Audigy MIDI/Game port (rev 04)
Subsystem: Creative Labs SB Audigy MIDI/Game Port
Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 32
Region 0: I/O ports at c800 [size=8]
Capabilities: [dc] Power Management version 2
Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 02 11 03 70 05 00 90 02 04 00 80 09 00 20 80 00
10: 01 c8 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 02 11 40 00
30: 00 00 00 00 dc 00 00 00 00 00 00 00 00 00 00 00
00:09.2 FireWire (IEEE 1394): Creative Labs SB Audigy FireWire Port (rev 04) (prog-if 10 [OHCI])
Subsystem: Creative Labs SB Audigy FireWire Port
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 32 (500ns min, 1000ns max), cache line size 08
Interrupt: pin B routed to IRQ 9
Region 0: Memory at eb104000 (32-bit, non-prefetchable) [size=2K]
Region 1: Memory at eb100000 (32-bit, non-prefetchable) [size=16K]
Capabilities: [44] Power Management version 2
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 02 11 01 40 06 00 10 02 04 10 00 0c 08 20 80 00
10: 00 40 10 eb 00 00 10 eb 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 02 11 10 00
30: 00 00 00 00 44 00 00 00 00 00 00 00 09 02 02 04
00:0a.0 PCI bridge: Digital Equipment Corporation DECchip 21152 (rev 03) (prog-if 00 [Normal decode])
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-
Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 32, cache line size 08
Bus: primary=00, secondary=02, subordinate=02, sec-latency=32
I/O behind bridge: 0000b000-0000bfff
Memory behind bridge: eb000000-eb0fffff
BridgeCtl: Parity- SERR+ NoISA+ VGA- MAbort- >Reset- FastB2B-
Capabilities: [dc] Power Management version 1
Flags: PMEClk- DSI- D1- D2- AuxCurrent=220mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Bridge: PM- B3+
00: 11 10 24 00 07 01 90 02 03 00 04 06 08 20 01 00
10: 00 00 00 00 00 00 00 00 00 02 02 20 b1 b1 80 02
20: 00 eb 00 eb f1 ff 01 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 dc 00 00 00 00 00 00 00 00 00 06 00
00:0b.0 Mass storage controller: Triones Technologies, Inc. HPT366/368/370/370A/372/372N (rev 04)
Subsystem: Triones Technologies, Inc. HPT370A
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 120 (2000ns min, 2000ns max), cache line size 08
Interrupt: pin A routed to IRQ 11
Region 0: I/O ports at d000 [size=8]
Region 1: I/O ports at d400 [size=4]
Region 2: I/O ports at d800 [size=8]
Region 3: I/O ports at dc00 [size=4]
Region 4: I/O ports at e000 [size=256]
Expansion ROM at 40000000 [disabled] [size=128K]
Capabilities: [60] Power Management version 2
Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 03 11 04 00 07 00 30 02 04 00 80 01 08 78 00 00
10: 01 d0 00 00 01 d4 00 00 01 d8 00 00 01 dc 00 00
20: 01 e0 00 00 00 00 00 00 00 00 00 00 03 11 01 00
30: 01 00 00 40 60 00 00 00 00 00 00 00 0b 01 08 08
01:00.0 VGA compatible controller: ATI Technologies Inc RV350 AP [Radeon 9600] (prog-if 00 [VGA])
Subsystem: PC Partner Limited: Unknown device 0200
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 32 (2000ns min), cache line size 08
Interrupt: pin A routed to IRQ 11
Region 0: Memory at c0000000 (32-bit, prefetchable) [size=256M]
Region 1: I/O ports at a000 [size=256]
Region 2: Memory at e9000000 (32-bit, non-prefetchable) [size=64K]
Expansion ROM at e8000000 [disabled] [size=128K]
Capabilities: [58] AGP version 2.0
Status: RQ=80 Iso- ArqSz=0 Cal=0 SBA+ ITACoh- GART64- HTrans- 64bit- FW+ AGP3- Rate=x1,x2,x4
Command: RQ=1 ArqSz=0 Cal=0 SBA+ AGP- GART64- 64bit- FW- Rate=<none>
Capabilities: [50] Power Management version 2
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 02 10 50 41 07 00 b0 02 00 00 00 03 08 20 80 00
10: 08 00 00 c0 01 a0 00 00 00 00 00 e9 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 4b 17 00 02
30: 00 00 00 e8 58 00 00 00 00 00 00 00 0b 01 08 00
01:00.1 Display controller: ATI Technologies Inc RV350 AP [Radeon 9600] (Secondary)
Subsystem: PC Partner Limited: Unknown device 0201
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 32 (2000ns min), cache line size 08
Region 0: Memory at d0000000 (32-bit, prefetchable) [size=256M]
Region 1: Memory at e9010000 (32-bit, non-prefetchable) [size=64K]
Capabilities: [50] Power Management version 2
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 02 10 70 41 07 00 b0 02 00 00 80 03 08 20 00 00
10: 08 00 00 d0 00 00 01 e9 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 4b 17 01 02
30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 08 00
02:04.0 Ethernet controller: Intel Corporation 8255xER/82551IT Fast Ethernet Controller (rev 09)
Subsystem: Matrox Graphics, Inc.: Unknown device 6000
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 32 (2000ns min, 14000ns max), cache line size 08
Interrupt: pin A routed to IRQ 10
Region 0: Memory at eb083000 (32-bit, non-prefetchable) [size=4K]
Region 1: I/O ports at b000 [size=64]
Region 2: Memory at eb000000 (32-bit, non-prefetchable) [size=128K]
Capabilities: [dc] Power Management version 2
Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=2 PME-
00: 86 80 09 12 07 00 90 02 09 00 00 02 08 20 00 00
10: 00 30 08 eb 01 b0 00 00 00 00 00 eb 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 2b 10 00 60
30: 00 00 00 00 dc 00 00 00 00 00 00 00 09 01 08 38
02:05.0 Ethernet controller: Intel Corporation 8255xER/82551IT Fast Ethernet Controller (rev 09)
Subsystem: Matrox Graphics, Inc.: Unknown device 6000
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 32 (2000ns min, 14000ns max), cache line size 08
Interrupt: pin A routed to IRQ 5
Region 0: Memory at eb081000 (32-bit, non-prefetchable) [size=4K]
Region 1: I/O ports at b400 [size=64]
Region 2: Memory at eb020000 (32-bit, non-prefetchable) [size=128K]
Capabilities: [dc] Power Management version 2
Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=2 PME-
00: 86 80 09 12 07 00 90 02 09 00 00 02 08 20 00 00
10: 00 10 08 eb 01 b4 00 00 00 00 02 eb 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 2b 10 00 60
30: 00 00 00 00 dc 00 00 00 00 00 00 00 05 01 08 38
02:06.0 Ethernet controller: Intel Corporation 8255xER/82551IT Fast Ethernet Controller (rev 09)
Subsystem: Matrox Graphics, Inc.: Unknown device 6000
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 32 (2000ns min, 14000ns max), cache line size 08
Interrupt: pin A routed to IRQ 11
Region 0: Memory at eb080000 (32-bit, non-prefetchable) [size=4K]
Region 1: I/O ports at b800 [size=64]
Region 2: Memory at eb040000 (32-bit, non-prefetchable) [size=128K]
Capabilities: [dc] Power Management version 2
Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=2 PME-
00: 86 80 09 12 07 00 90 02 09 00 00 02 08 20 00 00
10: 00 00 08 eb 01 b8 00 00 00 00 04 eb 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 2b 10 00 60
30: 00 00 00 00 dc 00 00 00 00 00 00 00 0b 01 08 38
02:07.0 Ethernet controller: Intel Corporation 8255xER/82551IT Fast Ethernet Controller (rev 09)
Subsystem: Matrox Graphics, Inc.: Unknown device 6000
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 32 (2000ns min, 14000ns max), cache line size 08
Interrupt: pin A routed to IRQ 10
Region 0: Memory at eb082000 (32-bit, non-prefetchable) [size=4K]
Region 1: I/O ports at bc00 [size=64]
Region 2: Memory at eb060000 (32-bit, non-prefetchable) [size=128K]
Capabilities: [dc] Power Management version 2
Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=2 PME-
00: 86 80 09 12 07 00 90 02 09 00 00 02 08 20 00 00
10: 00 20 08 eb 01 bc 00 00 00 00 06 eb 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 2b 10 00 60
30: 00 00 00 00 dc 00 00 00 00 00 00 00 0a 01 08 38
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: PCI bug in 2.6.13
2005-09-11 1:08 ` Miguel
@ 2005-09-11 1:41 ` Linus Torvalds
2005-09-11 8:53 ` Vojtech Pavlik
2005-09-11 14:10 ` Miguel
0 siblings, 2 replies; 15+ messages in thread
From: Linus Torvalds @ 2005-09-11 1:41 UTC (permalink / raw)
To: Miguel; +Cc: Andrew Morton, Linux Kernel Mailing List
On Sun, 11 Sep 2005, Miguel wrote:
>
> > > Also, what disk controller is this happening on?
>
> I'm not sure because I have a software RAID0 of 3x20GB, two hard disks
> are in the VIA controller and the other is in the onboard HPT370
> controller. Doing a diff between the lspci outputs there are some bytes
> different in the data of the HPT370 controller, maybe there is the
> problem.
It looks like your HPT controller.
00:0b.0 Mass storage controller: Triones Technologies, Inc. HPT366/368/370/370A/372/372N (rev 04)
...
-30: 01 00 00 40 60 00 00 00 00 00 00 00 0b 01 08 08
+30: 01 00 00 00 60 00 00 00 00 00 00 00 0b 01 08 08
That's a _really_ bad value. It's "enabled" (low bit set) but at address
zero in the bad case.
Can you double-check this same thing with the git snapshot (or 2.6.13.1)
that should have the pci_map_rom() thing fixed?
My problem is that I don't see what writes that invalid enable bit. The
patch that broke things for you explicitly avoids writing any value at
_all_, much less one with the rom enabled bit set (in fact, if the enabled
bit had been set, the patch wouldn't have made any difference at all for
you).
The HPT driver does some strange things:
/* FIXME: Not portable */
if (dev->resource[PCI_ROM_RESOURCE].start)
pci_write_config_byte(dev, PCI_ROM_ADDRESS,
dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
but that one too _explicitly_ only does so for non-zero resource start
values. But something clearly wrote 00000001 to your ROM address..
Can you try this _truly_ cheezy patch that should generate a stack trace
for the offending place? Btw, only do this with the 2.6.13.1 or git
kernels that have the fixed pci_map_rom(), otherwise you'll probably get
bogus traps for that case..
Linus
----
diff --git a/include/linux/pci.h b/include/linux/pci.h
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -377,6 +377,7 @@ static inline int pci_write_config_word(
}
static inline int pci_write_config_dword(struct pci_dev *dev, int where, u32 val)
{
+ WARN_ON(where == PCI_ROM_ADDRESS && val == 1);
return pci_bus_write_config_dword (dev->bus, dev->devfn, where, val);
}
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: PCI bug in 2.6.13
2005-09-11 1:41 ` Linus Torvalds
@ 2005-09-11 8:53 ` Vojtech Pavlik
2005-09-11 11:54 ` Linus Torvalds
2005-09-11 14:10 ` Miguel
1 sibling, 1 reply; 15+ messages in thread
From: Vojtech Pavlik @ 2005-09-11 8:53 UTC (permalink / raw)
To: Linus Torvalds; +Cc: Miguel, Andrew Morton, Linux Kernel Mailing List
On Sat, Sep 10, 2005 at 06:41:01PM -0700, Linus Torvalds wrote:
> It looks like your HPT controller.
>
> 00:0b.0 Mass storage controller: Triones Technologies, Inc. HPT366/368/370/370A/372/372N (rev 04)
> ...
> -30: 01 00 00 40 60 00 00 00 00 00 00 00 0b 01 08 08
> +30: 01 00 00 00 60 00 00 00 00 00 00 00 0b 01 08 08
>
> That's a _really_ bad value. It's "enabled" (low bit set) but at address
> zero in the bad case.
>
> My problem is that I don't see what writes that invalid enable bit. The
> patch that broke things for you explicitly avoids writing any value at
> _all_, much less one with the rom enabled bit set (in fact, if the enabled
> bit had been set, the patch wouldn't have made any difference at all for
> you).
>
> The HPT driver does some strange things:
>
> /* FIXME: Not portable */
> if (dev->resource[PCI_ROM_RESOURCE].start)
> pci_write_config_byte(dev, PCI_ROM_ADDRESS,
> dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
>
> but that one too _explicitly_ only does so for non-zero resource start
> values. But something clearly wrote 00000001 to your ROM address..
This is interesting. The 0x00000001 means that it's supposed to be an
unassigned I/O (!) space resource ... which obviously fools the if()
statement.
--
Vojtech Pavlik
SuSE Labs, SuSE CR
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: PCI bug in 2.6.13
2005-09-11 8:53 ` Vojtech Pavlik
@ 2005-09-11 11:54 ` Linus Torvalds
0 siblings, 0 replies; 15+ messages in thread
From: Linus Torvalds @ 2005-09-11 11:54 UTC (permalink / raw)
To: Vojtech Pavlik; +Cc: Miguel, Andrew Morton, Linux Kernel Mailing List
On Sun, 11 Sep 2005, Vojtech Pavlik wrote:
>
> This is interesting. The 0x00000001 means that it's supposed to be an
> unassigned I/O (!) space resource ... which obviously fools the if()
> statement.
No. ROM resources really are special. They are always MMIO, and the low
bit is used to specify whether they are "enabled" or not.
Yes, it's ugly as hell. Total special case.
Anyway, the resource value of 0x00000001 shouldn't fool the if-statement
at all, because when we fill in the resource "start" values, we correctly
mask off the status bits, and save those into the resource "flags". So
the PCI resource start should be 0, and that if-statement shouldn't have
triggered.
Linus
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: PCI bug in 2.6.13
2005-09-11 1:41 ` Linus Torvalds
2005-09-11 8:53 ` Vojtech Pavlik
@ 2005-09-11 14:10 ` Miguel
2005-09-11 16:08 ` Linus Torvalds
1 sibling, 1 reply; 15+ messages in thread
From: Miguel @ 2005-09-11 14:10 UTC (permalink / raw)
To: Linus Torvalds; +Cc: akpm, linux-kernel
Linus:
> Can you double-check this same thing with the git snapshot (or 2.6.13.1)
> that should have the pci_map_rom() thing fixed?
The diff between the working 2.6.13 and 2.6.13.1 is the same:
00:0b.0 Mass storage controller: Triones Technologies, Inc.
HPT366/368/370/370A/372/372N (rev 04)
...
-30: 01 00 00 40 60 00 00 00 00 00 00 00 0b 01 08 08
+30: 01 00 00 00 60 00 00 00 00 00 00 00 0b 01 08 08
Between 2.6.13 and 2.6.13-git10:
00:0b.0 Mass storage controller: Triones Technologies, Inc.
HPT366/368/370/370A/372/372N (rev 04)
...
- Expansion ROM at 40000000 [disabled] [size=128K]
+ Expansion ROM at 50000000 [disabled] [size=128K]
Capabilities: [60] Power Management version 2
Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME
(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 03 11 04 00 07 00 30 02 04 00 80 01 08 78 00 00
10: 01 d0 00 00 01 d4 00 00 01 d8 00 00 01 dc 00 00
20: 01 e0 00 00 00 00 00 00 00 00 00 00 03 11 01 00
-30: 01 00 00 40 60 00 00 00 00 00 00 00 0b 01 08 08
+30: 01 00 00 00 60 00 00 00 00 00 00 00 0b 01 08 08
> Can you try this _truly_ cheezy patch that should generate a stack trace
> for the offending place? Btw, only do this with the 2.6.13.1 or git
> kernels that have the fixed pci_map_rom(), otherwise you'll probably get
> bogus traps for that case..
After applying this patch I don't see anything new so I have added the
same WARN_ON in pci_write_config_byte and pci_write_config_word and now
dmesg shows this:
HPT370A: chipset revision 4
Badness in pci_write_config_byte at include/linux/pci.h:800
[<c025c519>]
[<c0269280>]
[<c02abbb9>]
[<c02692a7>]
[<c025ccf2>]
[<c0188043>]
[<c025cd48>]
[<c039e242>]
[<c039e278>]
[<c039e1e8>]
[<c03889c4>]
[<c0100383>]
[<c0100310>]
[<c0101125>]
HPT370A: 100% native mode on irq 11
HPT37X: using 33MHz PCI clock
ide2: BM-DMA at 0xe000-0xe007, BIOS settings: hde:DMA, hdf:pio
HPT37X: using 33MHz PCI clock
ide3: BM-DMA at 0xe008-0xe00f, BIOS settings: hdg:pio, hdh:pio
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: PCI bug in 2.6.13
2005-09-11 14:10 ` Miguel
@ 2005-09-11 16:08 ` Linus Torvalds
2005-09-11 16:30 ` Jeff Garzik
` (2 more replies)
0 siblings, 3 replies; 15+ messages in thread
From: Linus Torvalds @ 2005-09-11 16:08 UTC (permalink / raw)
To: Miguel; +Cc: akpm, linux-kernel
On Sun, 11 Sep 2005, Miguel wrote:
>
> After applying this patch I don't see anything new so I have added the
> same WARN_ON in pci_write_config_byte and pci_write_config_word and now
> dmesg shows this:
Thanks. Nobody should ever do a byte write to that offset, but clearly
something does.
And yes, that's what I missed even though I quoted it from the hpt366
driver (heh, and nobody else noticed either):
/* FIXME: Not portable */
if (dev->resource[PCI_ROM_RESOURCE].start)
pci_write_config_byte(dev, PCI_ROM_ADDRESS,
dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
I wonder how long that has been like that.
Change the pci_write_config_byte() into a pci_write_config_dword(), and I
bet it works.
However, I _also_ suspect it works if you remove those lines entirely. I
don't see why it tries to enable the ROM in the first place - it doesn't
seem to be _using_ it.
Linus
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: PCI bug in 2.6.13
2005-09-11 16:08 ` Linus Torvalds
@ 2005-09-11 16:30 ` Jeff Garzik
2005-09-11 17:15 ` Miguel
2005-09-12 17:20 ` Alan Cox
2 siblings, 0 replies; 15+ messages in thread
From: Jeff Garzik @ 2005-09-11 16:30 UTC (permalink / raw)
To: Linus Torvalds
Cc: Miguel, akpm, linux-kernel, Alan Cox, Bartlomiej Zolnierkiewicz
Linus Torvalds wrote:
>
> On Sun, 11 Sep 2005, Miguel wrote:
>
>>After applying this patch I don't see anything new so I have added the
>>same WARN_ON in pci_write_config_byte and pci_write_config_word and now
>>dmesg shows this:
>
>
> Thanks. Nobody should ever do a byte write to that offset, but clearly
> something does.
>
> And yes, that's what I missed even though I quoted it from the hpt366
> driver (heh, and nobody else noticed either):
>
> /* FIXME: Not portable */
> if (dev->resource[PCI_ROM_RESOURCE].start)
> pci_write_config_byte(dev, PCI_ROM_ADDRESS,
> dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
>
> I wonder how long that has been like that.
>
> Change the pci_write_config_byte() into a pci_write_config_dword(), and I
> bet it works.
>
> However, I _also_ suspect it works if you remove those lines entirely. I
> don't see why it tries to enable the ROM in the first place - it doesn't
> seem to be _using_ it.
I can't figure out what's going on in hpt driver, either. Just checked
in 2.2 (not present) and 2.4 (same write-byte code).
Maybe Alan or Bart has details?
Jeff
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: PCI bug in 2.6.13
2005-09-11 16:08 ` Linus Torvalds
2005-09-11 16:30 ` Jeff Garzik
@ 2005-09-11 17:15 ` Miguel
2005-09-11 17:59 ` Linus Torvalds
2005-09-12 17:20 ` Alan Cox
2 siblings, 1 reply; 15+ messages in thread
From: Miguel @ 2005-09-11 17:15 UTC (permalink / raw)
To: Linus Torvalds; +Cc: akpm, linux-kernel
Linus:
> Change the pci_write_config_byte() into a pci_write_config_dword(), and I
> bet it works.
It works!
> However, I _also_ suspect it works if you remove those lines entirely. I
> don't see why it tries to enable the ROM in the first place - it doesn't
> seem to be _using_ it.
I have also tried that and it works too.
Thank you.
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: PCI bug in 2.6.13
2005-09-11 17:15 ` Miguel
@ 2005-09-11 17:59 ` Linus Torvalds
0 siblings, 0 replies; 15+ messages in thread
From: Linus Torvalds @ 2005-09-11 17:59 UTC (permalink / raw)
To: Miguel; +Cc: akpm, linux-kernel
On Sun, 11 Sep 2005, Miguel wrote:
>
> I have also tried that and it works too.
>
> Thank you.
No, thank _you_. Disk corruption is a nasty nasty bug, and often very hard
to track down. The fact that you could pin-point it so well and were
willing to test different things out found a rather strange and subtle
bug.
This deserves to go into the -stable tree.
Linus
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: PCI bug in 2.6.13
2005-09-11 16:08 ` Linus Torvalds
2005-09-11 16:30 ` Jeff Garzik
2005-09-11 17:15 ` Miguel
@ 2005-09-12 17:20 ` Alan Cox
2 siblings, 0 replies; 15+ messages in thread
From: Alan Cox @ 2005-09-12 17:20 UTC (permalink / raw)
To: Linus Torvalds; +Cc: Miguel, akpm, linux-kernel
On Sul, 2005-09-11 at 09:08 -0700, Linus Torvalds wrote:
> if (dev->resource[PCI_ROM_RESOURCE].start)
> pci_write_config_byte(dev, PCI_ROM_ADDRESS,
> dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
>
> I wonder how long that has been like that.
Since before 2.2. I've no docs on why it does it though
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2005-09-12 16:55 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2005-09-09 16:04 PCI bug in 2.6.13 Miguel
2005-09-10 5:59 ` Andrew Morton
2005-09-10 9:36 ` Miguel
2005-09-10 16:51 ` Linus Torvalds
2005-09-10 21:06 ` Linus Torvalds
2005-09-11 1:08 ` Miguel
2005-09-11 1:41 ` Linus Torvalds
2005-09-11 8:53 ` Vojtech Pavlik
2005-09-11 11:54 ` Linus Torvalds
2005-09-11 14:10 ` Miguel
2005-09-11 16:08 ` Linus Torvalds
2005-09-11 16:30 ` Jeff Garzik
2005-09-11 17:15 ` Miguel
2005-09-11 17:59 ` Linus Torvalds
2005-09-12 17:20 ` Alan Cox
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