From: Arnd Bergmann <arnd@arndb.de>
To: Patrice Chotard <patrice.chotard@st.com>
Cc: Olof Johansson <olof@lixom.net>,
Kevin Hilman <khilman@baylibre.com>,
arm@kernel.org,
"open list:ARM/STI ARCHITECTURE" <kernel@stlinux.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [GIT PULL v2] STi SoC changes for v4.8
Date: Thu, 07 Jul 2016 15:23:25 +0200 [thread overview]
Message-ID: <11314287.lfBJrM5UFT@wuerfel> (raw)
In-Reply-To: <577E01B5.2030206@st.com>
On Thursday, July 7, 2016 9:16:05 AM CEST Patrice Chotard wrote:
> Highlights:
> -----------
> - Add a dummy L2 cache's write_sec callback as in non secure mode execution,
> we can't get access to L2 cache secure registers
> - Cosmetics change, in case of dump_stack, update the hardware name with a
> more generic for the STi SoCs family
>
This is also based on -rc5, please send a third version rebased to -rc3 or
earlier.
Arnd
next prev parent reply other threads:[~2016-07-07 13:20 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-07 7:16 [GIT PULL v2] STi SoC changes for v4.8 Patrice Chotard
2016-07-07 13:23 ` Arnd Bergmann [this message]
2016-07-11 7:38 ` Patrice Chotard
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