From: Lee Revell <rlrevell@joe-job.com>
To: Albert Cahalan <acahalan@gmail.com>
Cc: linux-kernel@vger.kernel.org, s0348365@sms.ed.ac.uk,
safemode@comcast.net
Subject: Re: athlon 64 dual core tsc out of sync
Date: Sat, 04 Feb 2006 21:08:26 -0500 [thread overview]
Message-ID: <1139105306.2791.83.camel@mindpipe> (raw)
In-Reply-To: <787b0d920602041745k65504414taaaef7f6d75b364c@mail.gmail.com>
On Sat, 2006-02-04 at 20:45 -0500, Albert Cahalan wrote:
> You clearly haven't been paying attention. Lots of computers vary the
> clock rate. They do this several ways.
I certainly have been paying attention. Most of these problems are
theoretical. In practice the only commonly used hardware where the TSC
is so unreliable as to be unusable are dual core Athlons.
Please check the jackit-devel (this app has tight RT constraints and
used to use the TSC directly for timing so problems show up quickly)
list for details - we have seen zero bug reports due to CPU frequency
scaling issues, and TONS related to the Athlon X2.
Lee
next prev parent reply other threads:[~2006-02-05 2:08 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-02-04 20:24 athlon 64 dual core tsc out of sync Albert Cahalan
2006-02-05 1:00 ` Lee Revell
2006-02-05 1:45 ` Albert Cahalan
2006-02-05 2:08 ` Lee Revell [this message]
2006-02-05 3:02 ` Ed Sweetman
2006-02-05 5:08 ` Alistair John Strachan
2006-02-05 2:24 ` Lee Revell
2006-02-05 5:06 ` Alistair John Strachan
-- strict thread matches above, loose matches on Subject: below --
2006-02-04 2:10 Ed Sweetman
2006-02-04 19:03 ` Lee Revell
2006-02-04 19:52 ` Alistair John Strachan
2006-02-04 21:55 ` Ed Sweetman
2006-02-04 19:16 ` Lee Revell
2006-02-05 16:32 ` Andi Kleen
2006-02-06 1:12 ` Ed Sweetman
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