Re: [PATCH for 2.6.18] [2/8] x86_64: On Intel systems when CPU has C3 don't use TSC

[Sergio Monteiro Basto <sergio@sergiomb.no-ip.org>]

On Sat, 2006-07-29 at 21:42 +0200, Andi Kleen wrote:
> On Intel systems generally the TSC stops in C3 or deeper, 
> so don't use it there. Follows similar logic on i386.
> 
> This should fix problems on Meroms.
> 
> Signed-off-by: Andi Kleen <ak@suse.de>
> 
...
> +	/* Most intel systems have synchronized TSCs except for
> +	   multi node systems */
> + 	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
> +#ifdef CONFIG_ACPI
> +		/* But TSC doesn't tick in C3 so don't use it there */
> +		if (acpi_fadt.length > 0 && acpi_fadt.plvl3_lat < 100)
> +			return 1;
> +#endif
> + 		return 0;
> +	}
> +
>   	/* Assume multi socket systems are not synchronized */
>   	return num_present_cpus() > 1;
>  }

Hi, 

I had some faith in this patch , but this just enable boot parameter
notsc (which I already use). And "just" disable tsc don't solve all the
problems. 

After "Using ACPI (MADT) for SMP configuration information"
my acpi_fadt.length is great than  0
acpi_fadt.plvl3_lat is 1001

On BIOS 1.40 update description of ASRock, claims this VIA chipset have
C1 stepping support.

this is a Pentium Dual Core on a 775Dual-880Pro
http://www.asrock.com/product/775Dual-880Pro.htm
http://bugme.osdl.org/show_bug.cgi?id=6419

Thanks,
Sérgio M. B.