From: Sergio Monteiro Basto <sergio@sergiomb.no-ip.org>
To: Andi Kleen <ak@suse.de>
Cc: discuss@x86-64.org, torvalds@osdl.org,
linux-kernel@vger.kernel.org, "Siddha,
Suresh B" <suresh.b.siddha@intel.com>
Subject: Re: [discuss] Re: [PATCH for 2.6.18] [2/8] x86_64: On Intel systems when CPU has C3 don't use TSC
Date: Tue, 01 Aug 2006 23:52:41 +0100 [thread overview]
Message-ID: <1154472761.3316.8.camel@localhost.portugal> (raw)
In-Reply-To: <200608020021.47623.ak@suse.de>
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ok , here it is dmesg version 16
I just add this printtk
--- linux-2.6.17.x86_64/arch/x86_64/kernel/time.c.orig 2006-08-01
01:34:29.000000000 +0100
+++ linux-2.6.17.x86_64/arch/x86_64/kernel/time.c 2006-08-01 23:31:29.000000000 +0100
@@ -959,6 +959,9 @@ __cpuinit int unsynchronized_tsc(void)
multi node systems */
if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
#ifdef CONFIG_ACPI
+ printk(KERN_INFO "time.c:SB acpi_fadt.length=%d, acpi_fadt.plvl3_lat=%d unsynchronized_tsc=%d\n",
+ acpi_fadt.length, acpi_fadt.plvl3_lat,(acpi_fadt.length > 0 && acpi_fadt.plvl3_lat <
+ 100) );
/* But TSC doesn't tick in C3 so don't use it there */
if (acpi_fadt.length > 0 && acpi_fadt.plvl3_lat < 100)
return 1;
but this time the function unsynchronized_tsc was just call one time.
time.c:SB acpi_fadt.length=0, acpi_fadt.plvl3_lat=0 unsynchronized_tsc=0
The patch works like I have use boot parameter notsc, which is better.
Now I don't need any parameter to boot.
Big Thanks
On Wed, 2006-08-02 at 00:21 +0200, Andi Kleen wrote:
> On Wednesday 02 August 2006 00:06, Sergio Monteiro Basto wrote:
> > On Tue, 2006-08-01 at 23:56 +0200, Andi Kleen wrote:
> > > Lost timer ticks print a rip. Do you have some samples?
>
> Can you send dmesg with the following patch applied too?
>
> cc'ing Suresh because he might have an explanation too then.
>
> -Andi
>
> Index: linux-2.6.18-rc3-work/arch/x86_64/kernel/smpboot.c
> ===================================================================
> --- linux-2.6.18-rc3-work.orig/arch/x86_64/kernel/smpboot.c
> +++ linux-2.6.18-rc3-work/arch/x86_64/kernel/smpboot.c
> @@ -345,7 +345,7 @@ static void __cpuinit tsc_sync_wait(void
> * mess up a possible perfect synchronization with a
> * not-quite-perfect algorithm.
> */
> - if (notscsync || !cpu_has_tsc || !unsynchronized_tsc())
> + if (0 && (notscsync || !cpu_has_tsc || !unsynchronized_tsc()))
> return;
> sync_tsc(0);
> }
--
Sérgio M. B.
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prev parent reply other threads:[~2006-08-01 22:52 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-07-29 19:42 [PATCH for 2.6.18] [2/8] x86_64: On Intel systems when CPU has C3 don't use TSC Andi Kleen
2006-08-01 13:04 ` Sergio Monteiro Basto
2006-08-01 17:10 ` [discuss] " Andi Kleen
2006-08-01 21:40 ` Sergio Monteiro Basto
2006-08-01 21:56 ` Andi Kleen
[not found] ` <1154470000.5123.1.camel@localhost.portugal>
2006-08-01 22:21 ` Andi Kleen
2006-08-01 22:52 ` Sergio Monteiro Basto [this message]
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