From: "Bryan O'Sullivan" <bos@serpentine.com>
To: Roland Dreier <rdreier@cisco.com>
Cc: Bill Waddington <william.waddington@beezmo.com>,
linux-kernel@vger.kernel.org
Subject: Re: Flushing writes to PCI devices
Date: Thu, 21 Sep 2006 14:04:00 -0700 [thread overview]
Message-ID: <1158872640.1996.9.camel@chalcedony.pathscale.com> (raw)
In-Reply-To: <adavenhgcpw.fsf@cisco.com>
On Thu, 2006-09-21 at 13:56 -0700, Roland Dreier wrote:
> Bryan> Yes. If your device requires that writes to some locations
> Bryan> in MMIO space be performed in a specific order, you must
> Bryan> explicitly do this in your driver. Intel CPUs will flush
> Bryan> posted writes out of order, for example.
>
> Really? Just normal posted PCI writes without using MTRRs or
> write-combining or anything like that?
No, not normal writes, but if you're writing to an area where you've
enabled write combining, it will happen (but not IIRC on AMD x86_64
CPUs). Sorry for the lack of clarity.
<b
next prev parent reply other threads:[~2006-09-21 21:04 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <fa.gbsNbubc34pqWPOxWCntrwUyt68@ifi.uio.no>
2006-09-20 18:28 ` Flushing writes to PCI devices Alan Stern
2006-09-20 19:10 ` linux-os (Dick Johnson)
[not found] ` <fa.V4O8HKrhUddxYm5+ixVbyZzPybE@ifi.uio.no>
2006-09-20 19:41 ` Bill Waddington
2006-09-20 20:17 ` linux-os (Dick Johnson)
2006-09-21 18:14 ` Bryan O'Sullivan
2006-09-21 18:45 ` Alan Cox
2006-09-21 20:56 ` Roland Dreier
2006-09-21 21:04 ` Bryan O'Sullivan [this message]
2006-09-20 22:39 ` Alan Cox
2006-09-20 23:22 ` Robert Hancock
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