Re: AMD X2 unsynced TSC fix?

[Sergio Monteiro Basto <sergio@sergiomb.no-ip.org>]

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On Sat, 2006-10-28 at 05:22 +0100, Sergio Monteiro Basto wrote:
> On Fri, 2006-10-27 at 21:06 -0700, Andi Kleen wrote:
> > > So far, has I can understand. Seems to me that my computer which have a
> > > Pentium D (Dual Core) on VIA chipset, also have unsynchronized TSC and
> > > with the patch of hrtimers on
> > 
> > Intel systems (except for some large highend systems) have synchronized TSCs. 
> > Only exception so far seems to be a few systems that are 
> > overclocked/overvolted and running outside their specification. 
> > When you do that you'e on your own and we're not interested in a bug
> > report.
> 
> and my computer :) 
> http://www.asrock.com/product/775Dual-880Pro.htm
> http://www.asrock.com/support/CPU_Support/show.asp?Model=775Dual-880Pro
> Monday I will checkout if my computer is under specs. 
> Seems that I like buy computers with many problems on Linux and fix :)

I bought this computer, on computers shop that have the best credits in
Portugal. And I don't change anything.

cat /proc/cpuinfo
processor       : 1
vendor_id       : GenuineIntel
cpu family      : 15
model           : 4
model name      :               Intel(R) Pentium(R) D CPU 2.80GHz
stepping        : 4
cpu MHz         : 2793.050
cache size      : 1024 KB

with 2 x 1024 KB cache size just saw Pentium D 820 in 
http://www.intel.com/products/processor_number/chart/pentium_d.htm

which is supported on
http://www.asrock.com/support/CPU_Support/show.asp?Model=775Dual-880Pro

775 Pentium D 820 2.80GHz 8O0MHz 2MB Smithfield All

Just see that don't have Enhanced Intel SpeedStep® Technology.

I attach here x86info which match with 
http://processorfinder.intel.com/details.aspx?sSpec=SL88T

Other curiosity with kernel 2.6.18.1 and the hrtimers patch. Kernel boot
oops and hang , if I don't give "notsc" option.




> 
> > There was also one BIOS found that had this problem, but it was old and rare
> > and got fixed with a upgrade.

I have last BIOS released 

> > 
> > > Just to point out. This could be more a problem of chipsets than CPUs
> > > (AMD or Intel). AMD just begin first using x86_64 archs :)
> > 
> > No.
> > 
> > -Andi

-- 
Sérgio M.B.

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x86info v1.17.  Dave Jones 2001-2005
Feedback to <davej@redhat.com>.

Found 2 CPUs
--------------------------------------------------------------------------
CPU #1
Found unknown cache descriptors: 81 91 96 
Family: 15 Model: 4 Stepping: 4 Type: 0 Brand: 0
CPU Model: Extreme Edition [A0]
Processor name string: Intel(R) Pentium(R) D CPU 2.80GHz

Feature flags:
 fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflsh ds acpi mmx fxsr sse sse2 ss ht tm pbe sse3 monitor ds-cpl cntx-id cx16 xTPR
Extended feature flags:
 SYSCALL em64t
L1 Data cache:
	Size: 16KB	Sectored, 8-way associative.
	line size=64 bytes.
Instruction TLB: 4K, 2MB or 4MB pages, fully associative, 128 entries.
Found unknown cache descriptors: 81 91 96 
Data TLB: 4KB or 4MB pages, fully associative, 64 entries.
Processor serial: 0000-0F44-0000-0000-0000-0000
The physical package supports 2 logical processors 

--------------------------------------------------------------------------
CPU #2
Found unknown cache descriptors: 81 91 96 
Family: 15 Model: 4 Stepping: 4 Type: 0 Brand: 0
CPU Model: Extreme Edition [A0]
Processor name string: Intel(R) Pentium(R) D CPU 2.80GHz

Feature flags:
 fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflsh ds acpi mmx fxsr sse sse2 ss ht tm pbe sse3 monitor ds-cpl cntx-id cx16 xTPR
Extended feature flags:
 SYSCALL em64t
L1 Data cache:
	Size: 16KB	Sectored, 8-way associative.
	line size=64 bytes.
Instruction TLB: 4K, 2MB or 4MB pages, fully associative, 128 entries.
Found unknown cache descriptors: 81 91 96 
Data TLB: 4KB or 4MB pages, fully associative, 64 entries.
Processor serial: 0000-0F44-0000-0000-0000-0000
The physical package supports 2 logical processors 

--------------------------------------------------------------------------

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