Re: serial flow control appears broken

Mark Lord
2007-08-02T14:57:28Z

Maciej W. Rozycki wrote:
> On Sat, 28 Jul 2007, Russell King wrote:
>
>> Essentially, any complex interrupt handler (such as an IDE interrupt
>> doing a multi-sector PIO transfer _in interrupt context_) can cause this
>> kind of starvation. That's why Linux 1.x had bottom halves - so that
>> the time consuming work could be moved out of the interrupt handler,
>> thereby causing minimal the blockage of other interrupts.
>>
>> Unfortunately, that kind of design has been long since forgotten.
>> Apparantly modern machines are fast enough that it doesn't have to be
>> worried about anymore... Or are they?
>
> I would guess it is not that the machines are fast enough, but that this
> two-level processing makes things more complicated. Enough that most
> people would not bother digging into it unless really forced. Only
> occasional latency problems are probably not enough of a force.

I don't believe the speed of the machine has much to do with it,
as IDE PIO is always at pretty much the same speed (or slower)
regardless of the CPU speed.

Best case is about .120 usec per 16-bit word, but that doesn't often pan out
in practice. More typical is something closer to 1 usec per 16-bit word.

So, for multcount=16 (very common), best case is 16 * 256 * .120 = 491 usec,
plus extra overhead for reading the IDE status register (another usec or so),
and other stuff. Figure maybe 500usec total per interrupt for multcount=16
in the best case, or 4000usec in the worst case.

At 115200bps, we get a byte every 86 usec or so. Assuming the UART FIFO
is set to interrupt (warn) us at 12/16 full, we have 4*86 = 344 usec to
respond and de-assert RTS. Less than that in practice.

Conclusion: using IDE multisector PIO is not a good idea with high speed
serial transfers happening, since we cannot respond quickly enough.

It might be possible to set the buffer underrun threshold lower in the UART (?).

All that said, I doubt that his system is using IDE PIO in the first place.
Dunno how long IDE DMA interrupts take, but it's probably in the 20-50 usec range.