* [PATCH 0/2] x86: MCE optimization and cleanups @ 2007-10-19 12:54 Joerg Roedel 2007-10-19 12:54 ` [PATCH 1/2] x86: MCE optimization/refactoring Joerg Roedel 2007-10-19 12:54 ` [PATCH 2/2] x86: mce minor indent cleanup Joerg Roedel 0 siblings, 2 replies; 4+ messages in thread From: Joerg Roedel @ 2007-10-19 12:54 UTC (permalink / raw) To: Thomas Gleixner; +Cc: linux-kernel This patchset includes two patches. 1. Checks for the MCA fetures as early as possible and signedness fixup. 2. Minor coding style cleanup. ^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 1/2] x86: MCE optimization/refactoring 2007-10-19 12:54 [PATCH 0/2] x86: MCE optimization and cleanups Joerg Roedel @ 2007-10-19 12:54 ` Joerg Roedel 2007-10-19 12:54 ` [PATCH 2/2] x86: mce minor indent cleanup Joerg Roedel 1 sibling, 0 replies; 4+ messages in thread From: Joerg Roedel @ 2007-10-19 12:54 UTC (permalink / raw) To: Thomas Gleixner; +Cc: linux-kernel, Joerg Roedel, Christoph Egger MCG_CAP never reports a negative count of available error-reporting banks. Therefore, make nr_mce_banks unsigned. Check for MCE feature bit as early as possible and clean up the extra _MCE checks in the various cpu init type functions per request from Thomas Gleixner. Signed-off-by: Christoph Egger <Christoph.Egger@amd.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> --- arch/x86/kernel/cpu/mcheck/k7.c | 6 +----- arch/x86/kernel/cpu/mcheck/mce.c | 12 ++++++++++-- arch/x86/kernel/cpu/mcheck/mce.h | 2 +- arch/x86/kernel/cpu/mcheck/p5.c | 4 ---- arch/x86/kernel/cpu/mcheck/p6.c | 4 ---- 5 files changed, 12 insertions(+), 16 deletions(-) diff --git a/arch/x86/kernel/cpu/mcheck/k7.c b/arch/x86/kernel/cpu/mcheck/k7.c index eef63e3..ad68cc9 100644 --- a/arch/x86/kernel/cpu/mcheck/k7.c +++ b/arch/x86/kernel/cpu/mcheck/k7.c @@ -72,13 +72,9 @@ void amd_mcheck_init(struct cpuinfo_x86 *c) u32 l, h; int i; - if (!cpu_has(c, X86_FEATURE_MCE)) - return; - machine_check_vector = k7_machine_check; wmb(); - printk (KERN_INFO "Intel machine check architecture supported.\n"); rdmsr (MSR_IA32_MCG_CAP, l, h); if (l & (1<<8)) /* Control register present ? */ wrmsr (MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); @@ -97,6 +93,6 @@ void amd_mcheck_init(struct cpuinfo_x86 *c) } set_in_cr4 (X86_CR4_MCE); - printk (KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n", + printk (KERN_INFO "CPU%d: AMD K7 machine check reporting enabled.\n", smp_processor_id()); } diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c index 34c781e..c7246cc 100644 --- a/arch/x86/kernel/cpu/mcheck/mce.c +++ b/arch/x86/kernel/cpu/mcheck/mce.c @@ -17,7 +17,7 @@ #include "mce.h" int mce_disabled = 0; -int nr_mce_banks; +unsigned int nr_mce_banks; EXPORT_SYMBOL_GPL(nr_mce_banks); /* non-fatal.o */ @@ -33,8 +33,16 @@ void fastcall (*machine_check_vector)(struct pt_regs *, long error_code) = unexp /* This has to be run for each processor */ void mcheck_init(struct cpuinfo_x86 *c) { - if (mce_disabled==1) + if (mce_disabled == 1) { + printk(KERN_INFO "MCE support disabled by bootparam\n"); return; + } + + if (!cpu_has(c, X86_FEATURE_MCE)) { + printk(KERN_INFO "CPU%i: No machine check support available\n", + smp_processor_id()); + return; + } switch (c->x86_vendor) { case X86_VENDOR_AMD: diff --git a/arch/x86/kernel/cpu/mcheck/mce.h b/arch/x86/kernel/cpu/mcheck/mce.h index 81fb6e2..9cbe812 100644 --- a/arch/x86/kernel/cpu/mcheck/mce.h +++ b/arch/x86/kernel/cpu/mcheck/mce.h @@ -10,5 +10,5 @@ void winchip_mcheck_init(struct cpuinfo_x86 *c); /* Call the installed machine check handler for this CPU setup. */ extern fastcall void (*machine_check_vector)(struct pt_regs *, long error_code); -extern int nr_mce_banks; +extern unsigned int nr_mce_banks; diff --git a/arch/x86/kernel/cpu/mcheck/p5.c b/arch/x86/kernel/cpu/mcheck/p5.c index 94bc43d..ddb41d2 100644 --- a/arch/x86/kernel/cpu/mcheck/p5.c +++ b/arch/x86/kernel/cpu/mcheck/p5.c @@ -32,10 +32,6 @@ void intel_p5_mcheck_init(struct cpuinfo_x86 *c) { u32 l, h; - /*Check for MCE support */ - if( !cpu_has(c, X86_FEATURE_MCE) ) - return; - /* Default P5 to off as its often misconnected */ if(mce_disabled != -1) return; diff --git a/arch/x86/kernel/cpu/mcheck/p6.c b/arch/x86/kernel/cpu/mcheck/p6.c index deeae42..be29c3c 100644 --- a/arch/x86/kernel/cpu/mcheck/p6.c +++ b/arch/x86/kernel/cpu/mcheck/p6.c @@ -84,10 +84,6 @@ void intel_p6_mcheck_init(struct cpuinfo_x86 *c) u32 l, h; int i; - /* Check for MCE support */ - if (!cpu_has(c, X86_FEATURE_MCE)) - return; - /* Check for PPro style MCA */ if (!cpu_has(c, X86_FEATURE_MCA)) return; -- 1.5.2.5 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] x86: mce minor indent cleanup 2007-10-19 12:54 [PATCH 0/2] x86: MCE optimization and cleanups Joerg Roedel 2007-10-19 12:54 ` [PATCH 1/2] x86: MCE optimization/refactoring Joerg Roedel @ 2007-10-19 12:54 ` Joerg Roedel 1 sibling, 0 replies; 4+ messages in thread From: Joerg Roedel @ 2007-10-19 12:54 UTC (permalink / raw) To: Thomas Gleixner; +Cc: linux-kernel, Joerg Roedel, Christoph Egger remove one indent level Signed-off-by: Christoph Egger <Christoph.Egger@amd.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> --- arch/x86/kernel/cpu/mcheck/mce.c | 40 +++++++++++++++++++------------------- 1 files changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c index c7246cc..e418c2f 100644 --- a/arch/x86/kernel/cpu/mcheck/mce.c +++ b/arch/x86/kernel/cpu/mcheck/mce.c @@ -45,26 +45,26 @@ void mcheck_init(struct cpuinfo_x86 *c) } switch (c->x86_vendor) { - case X86_VENDOR_AMD: - amd_mcheck_init(c); - break; - - case X86_VENDOR_INTEL: - if (c->x86==5) - intel_p5_mcheck_init(c); - if (c->x86==6) - intel_p6_mcheck_init(c); - if (c->x86==15) - intel_p4_mcheck_init(c); - break; - - case X86_VENDOR_CENTAUR: - if (c->x86==5) - winchip_mcheck_init(c); - break; - - default: - break; + case X86_VENDOR_AMD: + amd_mcheck_init(c); + break; + + case X86_VENDOR_INTEL: + if (c->x86==5) + intel_p5_mcheck_init(c); + if (c->x86==6) + intel_p6_mcheck_init(c); + if (c->x86==15) + intel_p4_mcheck_init(c); + break; + + case X86_VENDOR_CENTAUR: + if (c->x86==5) + winchip_mcheck_init(c); + break; + + default: + break; } } -- 1.5.2.5 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 0/2 try#4] x86: MCE optimization and cleanups @ 2007-10-15 12:16 Joerg Roedel 2007-10-15 12:16 ` [PATCH 1/2] x86: MCE optimization/refactoring Joerg Roedel 0 siblings, 1 reply; 4+ messages in thread From: Joerg Roedel @ 2007-10-15 12:16 UTC (permalink / raw) To: Thomas Gleixner; +Cc: Linux Kernel Mailing List This patchset includes two patches. 1. Checks for the MCA fetures as early as possible and signedness fixup. 2. Minor coding style cleanup. ^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 1/2] x86: MCE optimization/refactoring 2007-10-15 12:16 [PATCH 0/2 try#4] x86: MCE optimization and cleanups Joerg Roedel @ 2007-10-15 12:16 ` Joerg Roedel 0 siblings, 0 replies; 4+ messages in thread From: Joerg Roedel @ 2007-10-15 12:16 UTC (permalink / raw) To: Thomas Gleixner; +Cc: Linux Kernel Mailing List, Joerg Roedel, Christoph Egger MCG_CAP never reports a negative count of available error-reporting banks. Therefore, make nr_mce_banks unsigned. Check for MCE feature bit as early as possible and clean up the extra _MCE checks in the various cpu init type functions per request from Thomas Gleixner. Signed-off-by: Christoph Egger <Christoph.Egger@amd.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> --- arch/x86/kernel/cpu/mcheck/k7.c | 6 +----- arch/x86/kernel/cpu/mcheck/mce.c | 12 ++++++++++-- arch/x86/kernel/cpu/mcheck/mce.h | 2 +- arch/x86/kernel/cpu/mcheck/p5.c | 4 ---- arch/x86/kernel/cpu/mcheck/p6.c | 4 ---- 5 files changed, 12 insertions(+), 16 deletions(-) diff --git a/arch/x86/kernel/cpu/mcheck/k7.c b/arch/x86/kernel/cpu/mcheck/k7.c index eef63e3..ad68cc9 100644 --- a/arch/x86/kernel/cpu/mcheck/k7.c +++ b/arch/x86/kernel/cpu/mcheck/k7.c @@ -72,13 +72,9 @@ void amd_mcheck_init(struct cpuinfo_x86 *c) u32 l, h; int i; - if (!cpu_has(c, X86_FEATURE_MCE)) - return; - machine_check_vector = k7_machine_check; wmb(); - printk (KERN_INFO "Intel machine check architecture supported.\n"); rdmsr (MSR_IA32_MCG_CAP, l, h); if (l & (1<<8)) /* Control register present ? */ wrmsr (MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); @@ -97,6 +93,6 @@ void amd_mcheck_init(struct cpuinfo_x86 *c) } set_in_cr4 (X86_CR4_MCE); - printk (KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n", + printk (KERN_INFO "CPU%d: AMD K7 machine check reporting enabled.\n", smp_processor_id()); } diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c index 34c781e..c7246cc 100644 --- a/arch/x86/kernel/cpu/mcheck/mce.c +++ b/arch/x86/kernel/cpu/mcheck/mce.c @@ -17,7 +17,7 @@ #include "mce.h" int mce_disabled = 0; -int nr_mce_banks; +unsigned int nr_mce_banks; EXPORT_SYMBOL_GPL(nr_mce_banks); /* non-fatal.o */ @@ -33,8 +33,16 @@ void fastcall (*machine_check_vector)(struct pt_regs *, long error_code) = unexp /* This has to be run for each processor */ void mcheck_init(struct cpuinfo_x86 *c) { - if (mce_disabled==1) + if (mce_disabled == 1) { + printk(KERN_INFO "MCE support disabled by bootparam\n"); return; + } + + if (!cpu_has(c, X86_FEATURE_MCE)) { + printk(KERN_INFO "CPU%i: No machine check support available\n", + smp_processor_id()); + return; + } switch (c->x86_vendor) { case X86_VENDOR_AMD: diff --git a/arch/x86/kernel/cpu/mcheck/mce.h b/arch/x86/kernel/cpu/mcheck/mce.h index 81fb6e2..9cbe812 100644 --- a/arch/x86/kernel/cpu/mcheck/mce.h +++ b/arch/x86/kernel/cpu/mcheck/mce.h @@ -10,5 +10,5 @@ void winchip_mcheck_init(struct cpuinfo_x86 *c); /* Call the installed machine check handler for this CPU setup. */ extern fastcall void (*machine_check_vector)(struct pt_regs *, long error_code); -extern int nr_mce_banks; +extern unsigned int nr_mce_banks; diff --git a/arch/x86/kernel/cpu/mcheck/p5.c b/arch/x86/kernel/cpu/mcheck/p5.c index 94bc43d..ddb41d2 100644 --- a/arch/x86/kernel/cpu/mcheck/p5.c +++ b/arch/x86/kernel/cpu/mcheck/p5.c @@ -32,10 +32,6 @@ void intel_p5_mcheck_init(struct cpuinfo_x86 *c) { u32 l, h; - /*Check for MCE support */ - if( !cpu_has(c, X86_FEATURE_MCE) ) - return; - /* Default P5 to off as its often misconnected */ if(mce_disabled != -1) return; diff --git a/arch/x86/kernel/cpu/mcheck/p6.c b/arch/x86/kernel/cpu/mcheck/p6.c index deeae42..be29c3c 100644 --- a/arch/x86/kernel/cpu/mcheck/p6.c +++ b/arch/x86/kernel/cpu/mcheck/p6.c @@ -84,10 +84,6 @@ void intel_p6_mcheck_init(struct cpuinfo_x86 *c) u32 l, h; int i; - /* Check for MCE support */ - if (!cpu_has(c, X86_FEATURE_MCE)) - return; - /* Check for PPro style MCA */ if (!cpu_has(c, X86_FEATURE_MCA)) return; -- 1.5.2.5 ^ permalink raw reply related [flat|nested] 4+ messages in thread
end of thread, other threads:[~2007-10-19 12:57 UTC | newest] Thread overview: 4+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2007-10-19 12:54 [PATCH 0/2] x86: MCE optimization and cleanups Joerg Roedel 2007-10-19 12:54 ` [PATCH 1/2] x86: MCE optimization/refactoring Joerg Roedel 2007-10-19 12:54 ` [PATCH 2/2] x86: mce minor indent cleanup Joerg Roedel -- strict thread matches above, loose matches on Subject: below -- 2007-10-15 12:16 [PATCH 0/2 try#4] x86: MCE optimization and cleanups Joerg Roedel 2007-10-15 12:16 ` [PATCH 1/2] x86: MCE optimization/refactoring Joerg Roedel
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