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From: Dave Jiang <dave.jiang@intel.com>
To: Terry Bowman <terry.bowman@amd.com>, <alison.schofield@intel.com>,
	<vishal.l.verma@intel.com>, <ira.weiny@intel.com>,
	<bwidawsk@kernel.org>, <dan.j.williams@intel.com>,
	<Jonathan.Cameron@huawei.com>, <linux-cxl@vger.kernel.org>
Cc: <rrichter@amd.com>, <linux-kernel@vger.kernel.org>,
	<bhelgaas@google.com>
Subject: Re: [PATCH v6 18/27] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability
Date: Thu, 22 Jun 2023 17:03:53 -0700	[thread overview]
Message-ID: <11d4ef87-9724-dd61-e1b1-aef73afcef9f@intel.com> (raw)
In-Reply-To: <20230622035126.4130151-19-terry.bowman@amd.com>



On 6/21/23 20:51, Terry Bowman wrote:
> From: Robert Richter <rrichter@amd.com>
> 
> Now, that the Component Register mappings are stored, use them to
> enable and map the HDM decoder capabilities. The Component Registers
> do not need to be probed again for this, remove probing code.
> 
> The HDM capability applies to Endpoints, USPs and VH Host Bridges. The
> Endpoint's component register mappings are located in the cxlds and
> else in the port's structure. Provide a helper function
> cxl_port_get_comp_map() to locate the mappings depending on the
> component's type.
> 
> Signed-off-by: Robert Richter <rrichter@amd.com>
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> ---
>   drivers/cxl/core/hdm.c | 59 +++++++++++++++++++++---------------------
>   1 file changed, 30 insertions(+), 29 deletions(-)
> 
> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> index 5abfa9276dac..8dcd9f0b22d8 100644
> --- a/drivers/cxl/core/hdm.c
> +++ b/drivers/cxl/core/hdm.c
> @@ -81,26 +81,6 @@ static void parse_hdm_decoder_caps(struct cxl_hdm *cxlhdm)
>   		cxlhdm->interleave_mask |= GENMASK(14, 12);
>   }
>   
> -static int map_hdm_decoder_regs(struct cxl_port *port, void __iomem *crb,
> -				struct cxl_component_regs *regs)
> -{
> -	struct cxl_register_map map = {
> -		.dev = &port->dev,
> -		.resource = port->component_reg_phys,
> -		.base = crb,
> -		.max_size = CXL_COMPONENT_REG_BLOCK_SIZE,
> -	};
> -
> -	cxl_probe_component_regs(&port->dev, crb, &map.component_map);
> -	if (!map.component_map.hdm_decoder.valid) {
> -		dev_dbg(&port->dev, "HDM decoder registers not implemented\n");
> -		/* unique error code to indicate no HDM decoder capability */
> -		return -ENODEV;
> -	}
> -
> -	return cxl_map_component_regs(&map, regs, BIT(CXL_CM_CAP_CAP_ID_HDM));
> -}
> -
>   static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info)
>   {
>   	struct cxl_hdm *cxlhdm;
> @@ -145,6 +125,22 @@ static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info)
>   	return true;
>   }
>   
> +static struct cxl_register_map *cxl_port_get_comp_map(struct cxl_port *port)
> +{
> +	/*
> +	 * HDM capability applies to Endpoints, USPs and VH Host
> +	 * Bridges. The Endpoint's component register mappings are
> +	 * located in the cxlds.
> +	 */
> +	if (is_cxl_endpoint(port)) {
> +		struct cxl_memdev *memdev = to_cxl_memdev(port->uport_dev);
> +
> +		return &memdev->cxlds->comp_map;
> +	}
> +
> +	return &port->comp_map;
> +}
> +
>   /**
>    * devm_cxl_setup_hdm - map HDM decoder component registers
>    * @port: cxl_port to map
> @@ -155,7 +151,7 @@ struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port,
>   {
>   	struct device *dev = &port->dev;
>   	struct cxl_hdm *cxlhdm;
> -	void __iomem *crb;
> +	struct cxl_register_map *comp_map;
>   	int rc;
>   
>   	cxlhdm = devm_kzalloc(dev, sizeof(*cxlhdm), GFP_KERNEL);
> @@ -164,19 +160,24 @@ struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port,
>   	cxlhdm->port = port;
>   	dev_set_drvdata(dev, cxlhdm);
>   
> -	crb = ioremap(port->component_reg_phys, CXL_COMPONENT_REG_BLOCK_SIZE);
> -	if (!crb && info && info->mem_enabled) {
> -		cxlhdm->decoder_count = info->ranges;
> -		return cxlhdm;
> -	} else if (!crb) {
> +	comp_map = cxl_port_get_comp_map(port);
> +
> +	if (!comp_map->component_map.hdm_decoder.valid) {
> +		dev_dbg(&port->dev, "HDM decoder registers not found\n");
> +		if (info && info->mem_enabled) {
> +			cxlhdm->decoder_count = info->ranges;
> +			return cxlhdm;
> +		}
>   		dev_err(dev, "No component registers mapped\n");
>   		return ERR_PTR(-ENXIO);
>   	}
>   
> -	rc = map_hdm_decoder_regs(port, crb, &cxlhdm->regs);
> -	iounmap(crb);
> -	if (rc)
> +	rc = cxl_map_component_regs(comp_map, &cxlhdm->regs,
> +				    BIT(CXL_CM_CAP_CAP_ID_HDM));
> +	if (rc) {
> +		dev_dbg(dev, "Failed to map HDM capability.\n");
>   		return ERR_PTR(rc);
> +	}
>   
>   	parse_hdm_decoder_caps(cxlhdm);
>   	if (cxlhdm->decoder_count == 0) {

  reply	other threads:[~2023-06-23  0:04 UTC|newest]

Thread overview: 63+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-22  3:50 [PATCH v6 00/27] cxl/pci: Add support for RCH RAS error handling Terry Bowman
2023-06-22  3:51 ` [PATCH v6 01/27] cxl/port: Fix NULL pointer access in devm_cxl_add_port() Terry Bowman
2023-06-22  7:17   ` Robert Richter
2023-06-22  3:51 ` [PATCH v6 02/27] cxl/acpi: Probe RCRB later during RCH downstream port creation Terry Bowman
2023-06-22 22:36   ` Dave Jiang
2023-06-22  3:51 ` [PATCH v6 03/27] cxl: Updates for CXL Test to work with RCH Terry Bowman
2023-06-22  9:53   ` Jonathan Cameron
2023-06-22 10:03     ` Robert Richter
2023-06-22 14:02     ` Terry Bowman
2023-06-22 22:38   ` Dave Jiang
2023-06-22  3:51 ` [PATCH v6 04/27] cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability Terry Bowman
2023-06-22 22:51   ` Dave Jiang
2023-06-22  3:51 ` [PATCH v6 05/27] cxl: Rename member @dport of struct cxl_dport to @dport_dev Terry Bowman
2023-06-22  9:54   ` Jonathan Cameron
2023-06-22 22:53   ` Dave Jiang
2023-06-22  3:51 ` [PATCH v6 06/27] cxl: Rename 'uport' to 'uport_dev' Terry Bowman
2023-06-22  9:56   ` Jonathan Cameron
2023-06-22 22:54   ` Dave Jiang
2023-06-22  3:51 ` [PATCH v6 07/27] cxl/core/regs: Add @dev to cxl_register_map Terry Bowman
2023-06-22 11:14   ` Jonathan Cameron
2023-06-22 23:07   ` Dave Jiang
2023-06-22  3:51 ` [PATCH v6 08/27] cxl/pci: Refactor component register discovery for reuse Terry Bowman
2023-06-22 23:14   ` Dave Jiang
2023-06-22  3:51 ` [PATCH v6 09/27] cxl/acpi: Move add_host_bridge_uport() after cxl_get_chbs() Terry Bowman
2023-06-22 23:17   ` Dave Jiang
2023-06-22  3:51 ` [PATCH v6 10/27] cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's port Terry Bowman
2023-06-22 23:28   ` Dave Jiang
2023-06-22  3:51 ` [PATCH v6 11/27] cxl/port: Remove Component Register base address from struct cxl_dport Terry Bowman
2023-06-22 23:47   ` Dave Jiang
2023-06-22  3:51 ` [PATCH v6 12/27] cxl/regs: Remove early capability checks in Component Register setup Terry Bowman
2023-06-22 23:48   ` Dave Jiang
2023-06-22  3:51 ` [PATCH v6 13/27] cxl/mem: Prepare for early RCH dport component register setup Terry Bowman
2023-06-22 11:17   ` Jonathan Cameron
2023-06-22 23:50   ` Dave Jiang
2023-06-22  3:51 ` [PATCH v6 14/27] cxl/pci: Early setup RCH dport component registers from RCRB Terry Bowman
2023-06-22 23:58   ` Dave Jiang
2023-06-22  3:51 ` [PATCH v6 15/27] cxl/port: Store the port's Component Register mappings in struct cxl_port Terry Bowman
2023-06-22 13:20   ` Jonathan Cameron
2023-06-23  0:00   ` Dave Jiang
2023-06-22  3:51 ` [PATCH v6 16/27] cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport Terry Bowman
2023-06-23  0:01   ` Dave Jiang
2023-06-22  3:51 ` [PATCH v6 17/27] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state Terry Bowman
2023-06-23  0:02   ` Dave Jiang
2023-06-22  3:51 ` [PATCH v6 18/27] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability Terry Bowman
2023-06-23  0:03   ` Dave Jiang [this message]
2023-06-22  3:51 ` [PATCH v6 19/27] cxl/port: Remove Component Register base address from struct cxl_port Terry Bowman
2023-06-23  0:04   ` Dave Jiang
2023-06-22  3:51 ` [PATCH v6 20/27] cxl/pci: Add RCH downstream port AER register discovery Terry Bowman
2023-06-22 13:17   ` Jonathan Cameron
2023-06-23  0:10   ` Dave Jiang
2023-06-22  3:51 ` [PATCH v6 21/27] PCI/AER: Refactor cper_print_aer() for use by CXL driver module Terry Bowman
2023-06-22  3:51 ` [PATCH v6 22/27] cxl/pci: Update CXL error logging to use RAS register address Terry Bowman
2023-06-22  3:51 ` [PATCH v6 23/27] cxl/pci: Map RCH downstream AER registers for logging protocol errors Terry Bowman
2023-06-22 13:16   ` Jonathan Cameron
2023-06-22 14:42     ` Terry Bowman
2023-06-22  3:51 ` [PATCH v6 24/27] cxl/pci: Add RCH downstream port error logging Terry Bowman
2023-06-22  3:51 ` [PATCH v6 25/27] cxl/pci: Disable root port interrupts in RCH mode Terry Bowman
2023-06-22 13:12   ` Jonathan Cameron
2023-06-22 16:33     ` Terry Bowman
2023-06-23 13:28       ` Jonathan Cameron
2023-06-22  3:51 ` [PATCH v6 26/27] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler Terry Bowman
2023-06-22  3:51 ` [PATCH v6 27/27] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Terry Bowman
2023-06-22 13:07   ` Jonathan Cameron

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