Re: [patch] pci: revert "PCI: remove transparent bridge sizing"

[Benjamin Herrenschmidt <benh@kernel.crashing.org>]

> NOTE! This will also consider a bridge resource at 0 to be an invalid 
> resource (since now the alignment will be zero), which is a bit odd and 
> makes me worry a bit. I wouldn't be surprised if some non-PC architectures 
> have PCI bridges at zero. But maybe they should be (or already are?) 
> marked IORESOURCE_PCI_FIXED?

PCI bridges at zero is perfectly valid indeed and I'm sure we have that
around at least for IO space. In fact, I'm surprised you don't have that
on x86. Typically, things like an HT segment with a P2P bridge and
behind that bridge an ISA bridge could well have the P2P bridge with a
resource forwarding 0...0x1000 IO downstream for example even on x86
no ? (I'm not -that- familiar with the crazyness of legacy ISA on x86
but I've definitely seen such setup on other archs).

For MMIO, it mostly depends whether the code gets to work on raw bus
values, in which case 0 will be around, or already fixed up values (ie,
translated in CPU bus space) in which case 0 is unlikely.

In the case of pdev_sort_resources(), it will manipulate already fixed
up resources, so MMIO should work, but I'm a bit worried by PIO.

Ben.