From: "Huang, Ying" <ying.huang@intel.com>
To: dean gaudet <dean@arctic.org>
Cc: Sebastian Siewior <linux-crypto@ml.breakpoint.cc>,
Herbert Xu <herbert@gondor.apana.org.au>,
"Adam J. Richter" <adam@yggdrasil.com>,
akpm@linux-foundation.org, linux-kernel@vger.kernel.org,
linux-crypto@vger.kernel.org, mingo@elte.hu, tglx@linutronix.de
Subject: Re: [PATCH -mm crypto] AES: x86_64 asm implementation optimization
Date: Wed, 07 May 2008 13:12:14 +0800 [thread overview]
Message-ID: <1210137134.4676.1.camel@caritas-dev.intel.com> (raw)
In-Reply-To: <alpine.DEB.1.10.0805032323580.27385@twinlark.arctic.org>
[-- Attachment #1: Type: text/plain, Size: 935 bytes --]
Hi,
On Sat, 2008-05-03 at 23:25 -0700, dean gaudet wrote:
> one of the more important details in evaluating these changes would be the
> family/model/stepping of the processors being microbenchmarked... could
> you folks include /proc/cpuinfo with the results?
The file attached is /proc/cpuinfo of my testing machine.
Best Regards,
Huang Ying
> also -- please drop the #define for R16 to %rsp ... it obfuscates more
> than it helps anything.
>
> thanks
> -dean
>
> On Wed, 30 Apr 2008, Sebastian Siewior wrote:
>
> > * Huang, Ying | 2008-04-25 11:11:17 [+0800]:
> >
> > >Hi, Sebastian,
> > Hi Huang,
> >
> > sorry for the delay.
> >
> > >I changed the patches to group the read or write together instead of
> > >interleaving. Can you help me to test these new patches? The new patches
> > >is attached with the mail.
> > The new results are attached.
> >
> > >
> > >Best Regards,
> > >Huang Ying
> >
> > Sebastian
> >
[-- Attachment #2: cpuinfo --]
[-- Type: text/plain, Size: 1374 bytes --]
processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 15
model name : Intel(R) Core(TM)2 CPU 6400 @ 2.13GHz
stepping : 2
cpu MHz : 2128.006
cache size : 2048 KB
physical id : 0
siblings : 2
core id : 0
cpu cores : 2
fpu : yes
fpu_exception : yes
cpuid level : 10
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc arch_perfmon pebs bts rep_good pni monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr lahf_lm
bogomips : 4259.15
clflush size : 64
cache_alignment : 64
address sizes : 36 bits physical, 48 bits virtual
power management:
processor : 1
vendor_id : GenuineIntel
cpu family : 6
model : 15
model name : Intel(R) Core(TM)2 CPU 6400 @ 2.13GHz
stepping : 2
cpu MHz : 2128.006
cache size : 2048 KB
physical id : 0
siblings : 2
core id : 1
cpu cores : 2
fpu : yes
fpu_exception : yes
cpuid level : 10
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc arch_perfmon pebs bts rep_good pni monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr lahf_lm
bogomips : 4256.08
clflush size : 64
cache_alignment : 64
address sizes : 36 bits physical, 48 bits virtual
power management:
next prev parent reply other threads:[~2008-05-07 5:07 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-04-09 6:41 [PATCH -mm crypto] AES: x86_64 asm implementation optimization Huang, Ying
2008-04-16 7:31 ` Sebastian Siewior
2008-04-16 8:19 ` Huang, Ying
2008-04-16 8:23 ` Andi Kleen
2008-04-16 9:50 ` Herbert Xu
2008-04-16 18:40 ` Sebastian Siewior
2008-04-17 1:52 ` Huang, Ying
2008-04-17 3:34 ` Herbert Xu
2008-04-17 4:53 ` Huang, Ying
2008-04-23 22:28 ` Sebastian Siewior
2008-04-24 0:51 ` Herbert Xu
2008-04-17 3:36 ` Huang, Ying
2008-04-23 22:32 ` Sebastian Siewior
2008-04-25 3:11 ` Huang, Ying
2008-04-25 7:12 ` Sebastian Siewior
2008-04-25 7:21 ` Huang, Ying
2008-04-25 7:37 ` Sebastian Siewior
2008-04-29 22:12 ` Sebastian Siewior
2008-05-04 6:25 ` dean gaudet
2008-05-07 5:12 ` Huang, Ying [this message]
2008-05-07 5:26 ` Huang, Ying
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