[PATCH 1/2] x86: Move VMX MSRs to msr-index.h

[PATCH 1/2] x86: Move VMX MSRs to msr-index.h

[Sheng Yang]

They are hardware specific MSRs, and we would use them in virtualization
feature detection later.

Signed-off-by: Sheng Yang <sheng.yang@intel.com>
---
 arch/x86/kvm/vmx.h          |   15 ---------------
 include/asm-x86/msr-index.h |   16 ++++++++++++++++
 2 files changed, 16 insertions(+), 15 deletions(-)

diff --git a/arch/x86/kvm/vmx.h b/arch/x86/kvm/vmx.h
index 425a134..b32d4e5 100644
--- a/arch/x86/kvm/vmx.h
+++ b/arch/x86/kvm/vmx.h
@@ -331,21 +331,6 @@ enum vmcs_field {
 
 #define AR_RESERVD_MASK 0xfffe0f00
 
-#define MSR_IA32_VMX_BASIC                      0x480
-#define MSR_IA32_VMX_PINBASED_CTLS              0x481
-#define MSR_IA32_VMX_PROCBASED_CTLS             0x482
-#define MSR_IA32_VMX_EXIT_CTLS                  0x483
-#define MSR_IA32_VMX_ENTRY_CTLS                 0x484
-#define MSR_IA32_VMX_MISC                       0x485
-#define MSR_IA32_VMX_CR0_FIXED0                 0x486
-#define MSR_IA32_VMX_CR0_FIXED1                 0x487
-#define MSR_IA32_VMX_CR4_FIXED0                 0x488
-#define MSR_IA32_VMX_CR4_FIXED1                 0x489
-#define MSR_IA32_VMX_VMCS_ENUM                  0x48a
-#define MSR_IA32_VMX_PROCBASED_CTLS2            0x48b
-#define MSR_IA32_VMX_EPT_VPID_CAP               0x48c
-
-#define MSR_IA32_FEATURE_CONTROL                0x3a
 #define MSR_IA32_FEATURE_CONTROL_LOCKED         0x1
 #define MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED  0x4
 
diff --git a/include/asm-x86/msr-index.h b/include/asm-x86/msr-index.h
index 3052f05..0bb4330 100644
--- a/include/asm-x86/msr-index.h
+++ b/include/asm-x86/msr-index.h
@@ -176,6 +176,7 @@
 #define MSR_IA32_TSC			0x00000010
 #define MSR_IA32_PLATFORM_ID		0x00000017
 #define MSR_IA32_EBL_CR_POWERON		0x0000002a
+#define MSR_IA32_FEATURE_CONTROL        0x0000003a
 
 #define MSR_IA32_APICBASE		0x0000001b
 #define MSR_IA32_APICBASE_BSP		(1<<8)
@@ -310,4 +311,19 @@
 /* Geode defined MSRs */
 #define MSR_GEODE_BUSCONT_CONF0		0x00001900
 
+/* Intel VT MSRs */
+#define MSR_IA32_VMX_BASIC              0x00000480
+#define MSR_IA32_VMX_PINBASED_CTLS      0x00000481
+#define MSR_IA32_VMX_PROCBASED_CTLS     0x00000482
+#define MSR_IA32_VMX_EXIT_CTLS          0x00000483
+#define MSR_IA32_VMX_ENTRY_CTLS         0x00000484
+#define MSR_IA32_VMX_MISC               0x00000485
+#define MSR_IA32_VMX_CR0_FIXED0         0x00000486
+#define MSR_IA32_VMX_CR0_FIXED1         0x00000487
+#define MSR_IA32_VMX_CR4_FIXED0         0x00000488
+#define MSR_IA32_VMX_CR4_FIXED1         0x00000489
+#define MSR_IA32_VMX_VMCS_ENUM          0x0000048a
+#define MSR_IA32_VMX_PROCBASED_CTLS2    0x0000048b
+#define MSR_IA32_VMX_EPT_VPID_CAP       0x0000048c
+
 #endif /* ASM_X86__MSR_INDEX_H */
-- 
1.5.4.5

[PATCH 0/2] Extend "flags" to contain HW virtualization info

[Sheng Yang]

Hi, All

Here is the update version of "virt flags" according to comments. Now I
extend the "flags" instead of new "virt flags" line, this also result in
NCAPINTS was extended to 9.

Still just implement Intel side. And I don't mean to tell apart from VMX and
SVM features in cpufeatures.h.

Thanks!

--
regards
Yang, Sheng

[PATCH 1/2] x86: Move VMX MSRs to msr-index.h

[Sheng Yang]

They are hardware specific MSRs, and we would use them in virtualization
feature detection later.

Signed-off-by: Sheng Yang <sheng.yang@intel.com>
---
 arch/x86/kvm/vmx.h          |   15 ---------------
 include/asm-x86/msr-index.h |   16 ++++++++++++++++
 2 files changed, 16 insertions(+), 15 deletions(-)

diff --git a/arch/x86/kvm/vmx.h b/arch/x86/kvm/vmx.h
index 425a134..b32d4e5 100644
--- a/arch/x86/kvm/vmx.h
+++ b/arch/x86/kvm/vmx.h
@@ -331,21 +331,6 @@ enum vmcs_field {
 
 #define AR_RESERVD_MASK 0xfffe0f00
 
-#define MSR_IA32_VMX_BASIC                      0x480
-#define MSR_IA32_VMX_PINBASED_CTLS              0x481
-#define MSR_IA32_VMX_PROCBASED_CTLS             0x482
-#define MSR_IA32_VMX_EXIT_CTLS                  0x483
-#define MSR_IA32_VMX_ENTRY_CTLS                 0x484
-#define MSR_IA32_VMX_MISC                       0x485
-#define MSR_IA32_VMX_CR0_FIXED0                 0x486
-#define MSR_IA32_VMX_CR0_FIXED1                 0x487
-#define MSR_IA32_VMX_CR4_FIXED0                 0x488
-#define MSR_IA32_VMX_CR4_FIXED1                 0x489
-#define MSR_IA32_VMX_VMCS_ENUM                  0x48a
-#define MSR_IA32_VMX_PROCBASED_CTLS2            0x48b
-#define MSR_IA32_VMX_EPT_VPID_CAP               0x48c
-
-#define MSR_IA32_FEATURE_CONTROL                0x3a
 #define MSR_IA32_FEATURE_CONTROL_LOCKED         0x1
 #define MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED  0x4
 
diff --git a/include/asm-x86/msr-index.h b/include/asm-x86/msr-index.h
index 3052f05..0bb4330 100644
--- a/include/asm-x86/msr-index.h
+++ b/include/asm-x86/msr-index.h
@@ -176,6 +176,7 @@
 #define MSR_IA32_TSC			0x00000010
 #define MSR_IA32_PLATFORM_ID		0x00000017
 #define MSR_IA32_EBL_CR_POWERON		0x0000002a
+#define MSR_IA32_FEATURE_CONTROL        0x0000003a
 
 #define MSR_IA32_APICBASE		0x0000001b
 #define MSR_IA32_APICBASE_BSP		(1<<8)
@@ -310,4 +311,19 @@
 /* Geode defined MSRs */
 #define MSR_GEODE_BUSCONT_CONF0		0x00001900
 
+/* Intel VT MSRs */
+#define MSR_IA32_VMX_BASIC              0x00000480
+#define MSR_IA32_VMX_PINBASED_CTLS      0x00000481
+#define MSR_IA32_VMX_PROCBASED_CTLS     0x00000482
+#define MSR_IA32_VMX_EXIT_CTLS          0x00000483
+#define MSR_IA32_VMX_ENTRY_CTLS         0x00000484
+#define MSR_IA32_VMX_MISC               0x00000485
+#define MSR_IA32_VMX_CR0_FIXED0         0x00000486
+#define MSR_IA32_VMX_CR0_FIXED1         0x00000487
+#define MSR_IA32_VMX_CR4_FIXED0         0x00000488
+#define MSR_IA32_VMX_CR4_FIXED1         0x00000489
+#define MSR_IA32_VMX_VMCS_ENUM          0x0000048a
+#define MSR_IA32_VMX_PROCBASED_CTLS2    0x0000048b
+#define MSR_IA32_VMX_EPT_VPID_CAP       0x0000048c
+
 #endif /* ASM_X86__MSR_INDEX_H */
-- 
1.5.4.5

[PATCH 2/2] x86: Extended cpuinfo to show virtualization HW features

[Sheng Yang]

The hardware virtualization technology evolves very fast. But currently
it's hard to tell if your CPU support a certain kind of HW technology
without digging into the source code.

The patch add a new catagory in "flags" under /proc/cpuinfo. Now "flags"
can indicate the (important) HW virtulization features the CPU supported
as well.

Current implementation just cover Intel VMX side.

Signed-off-by: Sheng Yang <sheng.yang@intel.com>
---
 arch/x86/kernel/cpu/common.c |   45 ++++++++++++++++++++++++++++++++++++++++++
 include/asm-x86/cpufeature.h |    9 +++++++-
 2 files changed, 53 insertions(+), 1 deletions(-)

diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index f7c1964..01432e2 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -581,6 +581,50 @@ static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
 	}
 }
 
+static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
+{
+	/* Intel VMX MSR indicated features */
+#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW	0x00200000
+#define X86_VMX_FEATURE_PROC_CTLS_VNMI		0x00400000
+#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS	0x80000000
+#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC	0x00000001
+#define X86_VMX_FEATURE_PROC_CTLS2_EPT		0x00000002
+#define X86_VMX_FEATURE_PROC_CTLS2_VPID		0x00000020
+
+	u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
+
+	clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
+	clear_cpu_cap(c, X86_FEATURE_VNMI);
+	clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
+	clear_cpu_cap(c, X86_FEATURE_EPT);
+	clear_cpu_cap(c, X86_FEATURE_VPID);
+
+	rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
+	msr_ctl = vmx_msr_high | vmx_msr_low;
+	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
+		set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
+	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
+		set_cpu_cap(c, X86_FEATURE_VNMI);
+	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
+		rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
+		      vmx_msr_low, vmx_msr_high);
+		msr_ctl2 = vmx_msr_high | vmx_msr_low;
+		if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
+		    (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
+			set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
+		if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
+			set_cpu_cap(c, X86_FEATURE_EPT);
+		if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
+			set_cpu_cap(c, X86_FEATURE_VPID);
+	}
+}
+
+static void __cpuinit detect_virtcap(struct cpuinfo_x86 *c)
+{
+	if (cpu_has(c, X86_FEATURE_VMX))
+		detect_vmx_virtcap(c);
+}
+
 static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
 {
 	if (!have_cpuid_p())
@@ -613,6 +657,7 @@ static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
 
 	init_scattered_cpuid_features(c);
 	detect_nopl(c);
+	detect_virtcap(c);
 }
 
 /*
diff --git a/include/asm-x86/cpufeature.h b/include/asm-x86/cpufeature.h
index 7ac4d93..8d45690 100644
--- a/include/asm-x86/cpufeature.h
+++ b/include/asm-x86/cpufeature.h
@@ -6,7 +6,7 @@
 
 #include <asm/required-features.h>
 
-#define NCAPINTS	8	/* N 32-bit words worth of info */
+#define NCAPINTS	9	/* N 32-bit words worth of info */
 
 /*
  * Note: If the comment begins with a quoted string, that string is used
@@ -150,6 +150,13 @@
  */
 #define X86_FEATURE_IDA		(7*32+ 0) /* Intel Dynamic Acceleration */
 
+/* Virtualization flags: Linux defined */
+#define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */
+#define X86_FEATURE_VNMI        (8*32+ 1) /* Intel Virtual NMI */
+#define X86_FEATURE_FLEXPRIORITY (8*32+ 2) /* Intel FlexPriority */
+#define X86_FEATURE_EPT         (8*32+ 3) /* Intel Extended Page Table */
+#define X86_FEATURE_VPID        (8*32+ 4) /* Intel Virtual Processor ID */
+
 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
 
 #include <linux/bitops.h>
-- 
1.5.4.5

Re: [PATCH 2/2] x86: Extended cpuinfo to show virtualization HW features

[Yinghai Lu]

On Mon, Sep 8, 2008 at 11:54 PM, Sheng Yang <sheng.yang@intel.com> wrote:
> The hardware virtualization technology evolves very fast. But currently
> it's hard to tell if your CPU support a certain kind of HW technology
> without digging into the source code.
>
> The patch add a new catagory in "flags" under /proc/cpuinfo. Now "flags"
> can indicate the (important) HW virtulization features the CPU supported
> as well.
>
> Current implementation just cover Intel VMX side.
>
> Signed-off-by: Sheng Yang <sheng.yang@intel.com>
> ---
>  arch/x86/kernel/cpu/common.c |   45 ++++++++++++++++++++++++++++++++++++++++++
>  include/asm-x86/cpufeature.h |    9 +++++++-
>  2 files changed, 53 insertions(+), 1 deletions(-)
>
> diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
> index f7c1964..01432e2 100644
> --- a/arch/x86/kernel/cpu/common.c
> +++ b/arch/x86/kernel/cpu/common.c
> @@ -581,6 +581,50 @@ static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
>        }
>  }
>
> +static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
> +{
> +       /* Intel VMX MSR indicated features */
> +#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW   0x00200000
> +#define X86_VMX_FEATURE_PROC_CTLS_VNMI         0x00400000
> +#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS     0x80000000
> +#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC   0x00000001
> +#define X86_VMX_FEATURE_PROC_CTLS2_EPT         0x00000002
> +#define X86_VMX_FEATURE_PROC_CTLS2_VPID                0x00000020
> +
> +       u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
> +
> +       clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
> +       clear_cpu_cap(c, X86_FEATURE_VNMI);
> +       clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
> +       clear_cpu_cap(c, X86_FEATURE_EPT);
> +       clear_cpu_cap(c, X86_FEATURE_VPID);
> +
> +       rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
> +       msr_ctl = vmx_msr_high | vmx_msr_low;
> +       if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
> +               set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
> +       if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
> +               set_cpu_cap(c, X86_FEATURE_VNMI);
> +       if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
> +               rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
> +                     vmx_msr_low, vmx_msr_high);
> +               msr_ctl2 = vmx_msr_high | vmx_msr_low;
> +               if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
> +                   (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
> +                       set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
> +               if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
> +                       set_cpu_cap(c, X86_FEATURE_EPT);
> +               if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
> +                       set_cpu_cap(c, X86_FEATURE_VPID);
> +       }
> +}
> +
> +static void __cpuinit detect_virtcap(struct cpuinfo_x86 *c)
> +{
> +       if (cpu_has(c, X86_FEATURE_VMX))
> +               detect_vmx_virtcap(c);
> +}
> +
>  static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
>  {
>        if (!have_cpuid_p())
> @@ -613,6 +657,7 @@ static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
>
>        init_scattered_cpuid_features(c);
>        detect_nopl(c);
> +       detect_virtcap(c);

it should go into intel_64.c and intel.c

YH

Re: [PATCH 2/2] x86: Extended cpuinfo to show virtualization HW features

[Yang, Sheng]

On Tuesday 09 September 2008 15:52:26 Yinghai Lu wrote:
> On Mon, Sep 8, 2008 at 11:54 PM, Sheng Yang <sheng.yang@intel.com> wrote:
> > The hardware virtualization technology evolves very fast. But currently
> > it's hard to tell if your CPU support a certain kind of HW technology
> > without digging into the source code.
> >
> > The patch add a new catagory in "flags" under /proc/cpuinfo. Now "flags"
> > can indicate the (important) HW virtulization features the CPU supported
> > as well.
> >
> > Current implementation just cover Intel VMX side.
> >
> > Signed-off-by: Sheng Yang <sheng.yang@intel.com>
> > ---
> >  arch/x86/kernel/cpu/common.c |   45
> > ++++++++++++++++++++++++++++++++++++++++++ include/asm-x86/cpufeature.h |
> >    9 +++++++-
> >  2 files changed, 53 insertions(+), 1 deletions(-)
> >
> > diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
> > index f7c1964..01432e2 100644
> > --- a/arch/x86/kernel/cpu/common.c
> > +++ b/arch/x86/kernel/cpu/common.c
> > @@ -581,6 +581,50 @@ static void __cpuinit detect_nopl(struct cpuinfo_x86
> > *c) }
> >  }
> >
> > +static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
> > +{
> > +       /* Intel VMX MSR indicated features */
> > +#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW   0x00200000
> > +#define X86_VMX_FEATURE_PROC_CTLS_VNMI         0x00400000
> > +#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS     0x80000000
> > +#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC   0x00000001
> > +#define X86_VMX_FEATURE_PROC_CTLS2_EPT         0x00000002
> > +#define X86_VMX_FEATURE_PROC_CTLS2_VPID                0x00000020
> > +
> > +       u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
> > +
> > +       clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
> > +       clear_cpu_cap(c, X86_FEATURE_VNMI);
> > +       clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
> > +       clear_cpu_cap(c, X86_FEATURE_EPT);
> > +       clear_cpu_cap(c, X86_FEATURE_VPID);
> > +
> > +       rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
> > +       msr_ctl = vmx_msr_high | vmx_msr_low;
> > +       if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
> > +               set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
> > +       if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
> > +               set_cpu_cap(c, X86_FEATURE_VNMI);
> > +       if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
> > +               rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
> > +                     vmx_msr_low, vmx_msr_high);
> > +               msr_ctl2 = vmx_msr_high | vmx_msr_low;
> > +               if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
> > +                   (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
> > +                       set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
> > +               if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
> > +                       set_cpu_cap(c, X86_FEATURE_EPT);
> > +               if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
> > +                       set_cpu_cap(c, X86_FEATURE_VPID);
> > +       }
> > +}
> > +
> > +static void __cpuinit detect_virtcap(struct cpuinfo_x86 *c)
> > +{
> > +       if (cpu_has(c, X86_FEATURE_VMX))
> > +               detect_vmx_virtcap(c);
> > +}
> > +
> >  static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
> >  {
> >        if (!have_cpuid_p())
> > @@ -613,6 +657,7 @@ static void __cpuinit generic_identify(struct
> > cpuinfo_x86 *c)
> >
> >        init_scattered_cpuid_features(c);
> >        detect_nopl(c);
> > +       detect_virtcap(c);
>
> it should go into intel_64.c and intel.c
>
> YH

Yeah, I've considered that, but seems duplicate for both files? The feature 
detection code is the same. Any way to merge them? 

Thanks!
-- 
regards
Yang, Sheng

Re: [PATCH 2/2] x86: Extended cpuinfo to show virtualization HW features

[Avi Kivity]

Yang, Sheng wrote:
>> it should go into intel_64.c and intel.c
>>
>> YH
>>     
>
> Yeah, I've considered that, but seems duplicate for both files? The feature 
> detection code is the same. Any way to merge them? 
>   

You could add another file (intel-vt.c) and #include or link it from 
both intel.c and intel_64.c.

-- 
error compiling committee.c: too many arguments to function

Re: [PATCH 2/2] x86: Extended cpuinfo to show virtualization HW features

[Avi Kivity]

Sheng Yang wrote:
> The hardware virtualization technology evolves very fast. But currently
> it's hard to tell if your CPU support a certain kind of HW technology
> without digging into the source code.
>
> The patch add a new catagory in "flags" under /proc/cpuinfo. Now "flags"
> can indicate the (important) HW virtulization features the CPU supported
> as well.
>
> Current implementation just cover Intel VMX side.
>   

I'm missing the strings that go into /proc/cpuinfo?

-- 
error compiling committee.c: too many arguments to function

Re: [PATCH 1/2] x86: Move VMX MSRs to msr-index.h

[Avi Kivity]

Sheng Yang wrote:
> They are hardware specific MSRs, and we would use them in virtualization
> feature detection later.
>
>   


> -
> -#define MSR_IA32_FEATURE_CONTROL                0x3a
>  #define MSR_IA32_FEATURE_CONTROL_LOCKED         0x1
>  #define MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED  0x

Might as well move these two bitmask definitions.


-- 
error compiling committee.c: too many arguments to function

Re: [PATCH 2/2] x86: Extended cpuinfo to show virtualization HW features

[H. Peter Anvin]

Avi Kivity wrote:
> 
> I'm missing the strings that go into /proc/cpuinfo?
> 

Those are autogenerated now.

	-hpa

Re: [PATCH 2/2] x86: Extended cpuinfo to show virtualization HW features

[Yinghai Lu]

On Tue, Sep 9, 2008 at 1:05 AM, Yang, Sheng <sheng.yang@intel.com> wrote:
>
> Yeah, I've considered that, but seems duplicate for both files? The feature
> detection code is the same. Any way to merge them?
>

just merged intel_64.c into intel.c...

YH

Re: [PATCH 2/2] x86: Extended cpuinfo to show virtualization HW features

[Ingo Molnar]

* Yinghai Lu <yhlu.kernel@gmail.com> wrote:

> On Tue, Sep 9, 2008 at 1:05 AM, Yang, Sheng <sheng.yang@intel.com> wrote:
> >
> > Yeah, I've considered that, but seems duplicate for both files? The feature
> > detection code is the same. Any way to merge them?
> 
> just merged intel_64.c into intel.c...

it's all in tip/master:

  http://people.redhat.com/mingo/tip.git/README

would it be possible to get a patchset ontop of that?

	Ingo

Re: [PATCH 2/2] x86: Extended cpuinfo to show virtualization HW features

[Yang, Sheng]

On Wednesday 10 September 2008 16:04:21 Ingo Molnar wrote:
> * Yinghai Lu <yhlu.kernel@gmail.com> wrote:
> > On Tue, Sep 9, 2008 at 1:05 AM, Yang, Sheng <sheng.yang@intel.com> wrote:
> > > Yeah, I've considered that, but seems duplicate for both files? The
> > > feature detection code is the same. Any way to merge them?
> >
> > just merged intel_64.c into intel.c...
>
> it's all in tip/master:
>
>   http://people.redhat.com/mingo/tip.git/README
>
> would it be possible to get a patchset ontop of that?
>
> 	Ingo

So quick.... 
Thanks Yinghai!

Would send the updated patch soon.
-- 
regards
Yang, Sheng

Re: [PATCH 1/2] x86: Move VMX MSRs to msr-index.h

[Yang, Sheng]

On Tuesday 09 September 2008 21:47:03 Avi Kivity wrote:
> Sheng Yang wrote:
> > They are hardware specific MSRs, and we would use them in virtualization
> > feature detection later.
> >
> >
> >
> >
> > -
> > -#define MSR_IA32_FEATURE_CONTROL                0x3a
> >  #define MSR_IA32_FEATURE_CONTROL_LOCKED         0x1
> >  #define MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED  0x
>
> Might as well move these two bitmask definitions.

Um... I think it's better to leave them here, for the MSR_IA32_FEATURE_CONTROL 
is a MSR which can be put into msr-index.h, but the others are only bits of 
MSR...

-- 
regards
Yang, Sheng

[PATCH 2/2] x86: Extended "flags" to show virtualization HW feature in /proc/cpuinfo

[Sheng Yang]

The hardware virtualization technology evolves very fast. But currently
it's hard to tell if your CPU support a certain kind of HW technology
without digging into the source code.

The patch add a new catagory in "flags" under /proc/cpuinfo. Now "flags"
can indicate the (important) HW virtulization features the CPU supported
as well.

Current implementation just cover Intel VMX side.

Signed-off-by: Sheng Yang <sheng.yang@intel.com>
---
 arch/x86/kernel/cpu/intel.c  |   41 +++++++++++++++++++++++++++++++++++++++++
 include/asm-x86/cpufeature.h |    9 ++++++++-
 2 files changed, 49 insertions(+), 1 deletions(-)

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 5f76bf1..99468db 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -196,6 +196,44 @@ static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
 		return 1;
 }
 
+static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
+{
+	/* Intel VMX MSR indicated features */
+#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW	0x00200000
+#define X86_VMX_FEATURE_PROC_CTLS_VNMI		0x00400000
+#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS	0x80000000
+#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC	0x00000001
+#define X86_VMX_FEATURE_PROC_CTLS2_EPT		0x00000002
+#define X86_VMX_FEATURE_PROC_CTLS2_VPID		0x00000020
+
+	u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
+
+	clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
+	clear_cpu_cap(c, X86_FEATURE_VNMI);
+	clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
+	clear_cpu_cap(c, X86_FEATURE_EPT);
+	clear_cpu_cap(c, X86_FEATURE_VPID);
+
+	rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
+	msr_ctl = vmx_msr_high | vmx_msr_low;
+	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
+		set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
+	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
+		set_cpu_cap(c, X86_FEATURE_VNMI);
+	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
+		rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
+		      vmx_msr_low, vmx_msr_high);
+		msr_ctl2 = vmx_msr_high | vmx_msr_low;
+		if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
+		    (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
+			set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
+		if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
+			set_cpu_cap(c, X86_FEATURE_EPT);
+		if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
+			set_cpu_cap(c, X86_FEATURE_VPID);
+	}
+}
+
 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 {
 	unsigned int l2 = 0;
@@ -289,6 +327,9 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 
 	/* Work around errata */
 	srat_detect_node();
+
+	if (cpu_has(c, X86_FEATURE_VMX))
+		detect_vmx_virtcap(c);
 }
 
 #ifdef CONFIG_X86_32
diff --git a/include/asm-x86/cpufeature.h b/include/asm-x86/cpufeature.h
index 7ac4d93..8d45690 100644
--- a/include/asm-x86/cpufeature.h
+++ b/include/asm-x86/cpufeature.h
@@ -6,7 +6,7 @@
 
 #include <asm/required-features.h>
 
-#define NCAPINTS	8	/* N 32-bit words worth of info */
+#define NCAPINTS	9	/* N 32-bit words worth of info */
 
 /*
  * Note: If the comment begins with a quoted string, that string is used
@@ -150,6 +150,13 @@
  */
 #define X86_FEATURE_IDA		(7*32+ 0) /* Intel Dynamic Acceleration */
 
+/* Virtualization flags: Linux defined */
+#define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */
+#define X86_FEATURE_VNMI        (8*32+ 1) /* Intel Virtual NMI */
+#define X86_FEATURE_FLEXPRIORITY (8*32+ 2) /* Intel FlexPriority */
+#define X86_FEATURE_EPT         (8*32+ 3) /* Intel Extended Page Table */
+#define X86_FEATURE_VPID        (8*32+ 4) /* Intel Virtual Processor ID */
+
 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
 
 #include <linux/bitops.h>
-- 
1.5.4.5

Re: [PATCH 2/2] x86: Extended cpuinfo to show virtualization HW features

[Ingo Molnar]

* Yang, Sheng <sheng.yang@intel.com> wrote:

> On Wednesday 10 September 2008 16:04:21 Ingo Molnar wrote:
> > * Yinghai Lu <yhlu.kernel@gmail.com> wrote:
> > > On Tue, Sep 9, 2008 at 1:05 AM, Yang, Sheng <sheng.yang@intel.com> wrote:
> > > > Yeah, I've considered that, but seems duplicate for both files? The
> > > > feature detection code is the same. Any way to merge them?
> > >
> > > just merged intel_64.c into intel.c...
> >
> > it's all in tip/master:
> >
> >   http://people.redhat.com/mingo/tip.git/README
> >
> > would it be possible to get a patchset ontop of that?
> >
> > 	Ingo
> 
> So quick.... 

hey, wasting time is something we really suck at ;-)

> Thanks Yinghai!
> 
> Would send the updated patch soon.

got it, thanks. I've applied patch #1 and updated patch #2 to the 
tip/x86/unify-cpu-detect topic tree:

 e38e05a: x86: extended "flags" to show virtualization HW feature in /proc/cpuinfo
 315a655: x86: move VMX MSRs to msr-index.h

	Ingo

Re: [PATCH 1/2] x86: Move VMX MSRs to msr-index.h

[Avi Kivity]

Yang, Sheng wrote:
> On Tuesday 09 September 2008 21:47:03 Avi Kivity wrote:
>   
>> Sheng Yang wrote:
>>     
>>> They are hardware specific MSRs, and we would use them in virtualization
>>> feature detection later.
>>>
>>>
>>>
>>>
>>> -
>>> -#define MSR_IA32_FEATURE_CONTROL                0x3a
>>>  #define MSR_IA32_FEATURE_CONTROL_LOCKED         0x1
>>>  #define MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED  0x
>>>       
>> Might as well move these two bitmask definitions.
>>     
>
> Um... I think it's better to leave them here, for the MSR_IA32_FEATURE_CONTROL 
> is a MSR which can be put into msr-index.h, but the others are only bits of 
> MSR...
>   

The EFER bits are in msr-index.h, and I think the msr index in one file 
and the bits in another detract from clarity.

-- 
error compiling committee.c: too many arguments to function

Re: [PATCH 1/2] x86: Move VMX MSRs to msr-index.h

[Yang, Sheng]

On Wednesday 10 September 2008 22:30:15 Avi Kivity wrote:
> Yang, Sheng wrote:
> > On Tuesday 09 September 2008 21:47:03 Avi Kivity wrote:
> >> Sheng Yang wrote:
> >>> They are hardware specific MSRs, and we would use them in
> >>> virtualization feature detection later.
> >>>
> >>>
> >>>
> >>>
> >>> -
> >>> -#define MSR_IA32_FEATURE_CONTROL                0x3a
> >>>  #define MSR_IA32_FEATURE_CONTROL_LOCKED         0x1
> >>>  #define MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED  0x
> >>
> >> Might as well move these two bitmask definitions.
> >
> > Um... I think it's better to leave them here, for the
> > MSR_IA32_FEATURE_CONTROL is a MSR which can be put into msr-index.h, but
> > the others are only bits of MSR...
>
> The EFER bits are in msr-index.h, and I think the msr index in one file
> and the bits in another detract from clarity.

I agree now, sorry for miss that... 

Would post another patch(es) to do this clean up...

-- 
regards
Yang, Sheng