Re: [PATCH 3/3] perf_counter: powerpc: supply more precise information on counter overflow events

[Peter Zijlstra <a.p.zijlstra@chello.nl>]

On Thu, 2009-05-14 at 13:31 +1000, Paul Mackerras wrote:
> This uses values from the MMCRA, SIAR and SDAR registers on powerpc to
> supply more precise information for overflow events, including a data
> address when PERF_RECORD_ADDR is specified.
> 
> Since POWER6 uses different bit positions in MMCRA from earlier processors,
> this converts the struct power_pmu limited_pmc5_6 field, which only had
> 0/1 values, into a flags field and defines bit values for its previous
> use (PPMU_LIMITED_PMC5_6) and a new flag (PPMU_ALT_SIPR) to indicate
> that the processor uses the POWER6 bit positions rather than the earlier
> positions.  It also adds definitions in reg.h for the new and old positions
> of the bit that indicates that the SIAR and SDAR values come from the
> same instruction.
> 
> For the data address, the SDAR value is supplied if we are not doing
> instruction sampling.  In that case there is no guarantee that the address
> given in the PERF_RECORD_ADDR subrecord will correspond to the instruction
> whose address is given in the PERF_RECORD_IP subrecord.
> 
> If instruction sampling is enabled (e.g. because this counter is counting
> a marked instruction event), then we only supply the SDAR value for the
> PERF_RECORD_ADDR subrecord if it corresponds to the instruction whose
> address is in the PERF_RECORD_IP subrecord.  Otherwise we supply 0.

Very cool hardware feature! :-)