Re: [perfmon2] comments on Performance Counters for Linux (PCL)

[Carl Love <cel@us.ibm.com>]

On Fri, 2009-05-29 at 10:21 +0200, Geert Uytterhoeven wrote:
> On Fri, 29 May 2009, Ingo Molnar wrote:
> > * Paul Mackerras <paulus@samba.org> wrote:
> > > Ingo Molnar writes:
> > > > * Corey Ashford <cjashfor@linux.vnet.ibm.com> wrote:
> > > > >> So you're suggesting to artificually strech periods by say 
> > > > >> composing a single overflow from smaller ones, ignoring the 
> > > > >> intermediate overflow events?
> > > > >>
> > > > >> That sounds doable, again, patch welcome.
> > > > >
> > > > > I definitely agree with Stephane's point on this one.  I had 
> > > > > assumed that long irq_periods (longer than the width of the 
> > > > > counter) would be synthesized as you suggest.  If this is not the 
> > > > > case, PCL should be changed so that it does, -or- at a minimum, 
> > > > > the user should get an error back stating that the period is too 
> > > > > long for the hardware counter.
> > > > 
> > > > this looks somewhat academic - at least on x86, even the fastest 
> > > > events (say cycles) with a 32 bit overflow means one event per 
> > > > second on 4GB. That's not a significant event count in practice. 
> > > > What's the minimum width we are talking about on Power?
> > > 
> > > 32 bits, but since the top bit is effectively a level-sensitive 
> > > interrupt request, the maximum period in hardware is 2^31 counts.
> > > 
> > > However, I already support 64-bit interrupt periods (well, 63-bit 
> > > actually) on powerpc by only calling perf_counter_overflow() when 
> > > counter->hw.period_left becomes <= 0, and arranging to set the 
> > > hardware counter to 0 if counter->hw.period_left is >= 0x80000000. 
> > > It's a tiny amount of code to handle it, really.
> > 
> > No argument about that - just wanted to know whether there's any 
> > real practical effect beyond the nitpicking factor ;-)
> 
> I never really dived into this stuff, but ISTR there are some 16-bit counters
> on CELL? Is that correct?

FYI, the counters on CELL are configurable.  You can have up to eight 16
bit count counters or you can combine counters i and i=1 (where
i=0,2,4,6) into 32 bit counters.  This allows you to have some 16 and
some 32 bit counters at the same time.  

> 
> With kind regards,
> 
> Geert Uytterhoeven
> Software Architect
> Techsoft Centre
> 
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