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From: Peter Zijlstra <a.p.zijlstra@chello.nl>
To: Yong Wang <yong.y.wang@linux.intel.com>
Cc: eranian@gmail.com, "Wang, Yong Y" <yong.y.wang@intel.com>,
	Ingo Molnar <mingo@elte.hu>, LKML <linux-kernel@vger.kernel.org>,
	Paul Mackerras <paulus@samba.org>,
	Andi Kleen <andi@firstfloor.org>
Subject: Re: perf_counter Atom patch
Date: Tue, 23 Jun 2009 11:10:05 +0200	[thread overview]
Message-ID: <1245748205.19816.1550.camel@twins> (raw)
In-Reply-To: <20090623083420.GB23534@ywang-moblin2.bj.intel.com>

On Tue, 2009-06-23 at 16:34 +0800, Yong Wang wrote:
> > you could simply consider having 0 fixed counters and everything else would work
> > as expected. But there is a catch, unfortunately, in that there is erratum AE49
> > which says that there is only one enable bit to control the two generic counters
> > on Core Duo/Solo.

Ah, that's similar to P6 like machines. The P6 docs say that to disable
a counter you should simply write all zeros (except the EN bit for ctr0)
to the control register (IIRC).

I suppose we could do something similar on these errata cores, make
x86_pmu_disable_counter() write ARCH_PERFMON_EVENTSEL0_ENABLE instead.

Would that work?


  reply	other threads:[~2009-06-23  9:10 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2009-06-22 20:26 perf_counter Atom patch stephane eranian
2009-06-23  3:38 ` Wang, Yong Y
2009-06-23  7:45   ` stephane eranian
2009-06-23  7:59     ` Yong Wang
2009-06-23  8:27       ` stephane eranian
2009-06-23  8:34         ` Yong Wang
2009-06-23  9:10           ` Peter Zijlstra [this message]
2009-06-23  9:40             ` stephane eranian
2009-06-23  8:40         ` stephane eranian
2009-06-23  8:53           ` Yong Wang
2009-06-23  9:19             ` stephane eranian
2009-06-23  9:47             ` Ingo Molnar
2009-06-24  2:19               ` Yong Wang
2009-06-24  8:52                 ` Ingo Molnar
2009-06-25 10:39                   ` stephane eranian
2009-06-23  5:59 ` Wang, Yong Y

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