From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754797AbZHNKez (ORCPT ); Fri, 14 Aug 2009 06:34:55 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1753676AbZHNKey (ORCPT ); Fri, 14 Aug 2009 06:34:54 -0400 Received: from hera.kernel.org ([140.211.167.34]:37509 "EHLO hera.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752663AbZHNKey (ORCPT ); Fri, 14 Aug 2009 06:34:54 -0400 Subject: [PATCH V2] X86: Fix x86_cache_size value From: Jaswinder Singh Rajput To: x86 maintainers Cc: LKML In-Reply-To: <1250245149.9062.3.camel@ht.satnam> References: <1250245149.9062.3.camel@ht.satnam> Content-Type: text/plain Date: Fri, 14 Aug 2009 16:03:56 +0530 Message-Id: <1250246036.9062.5.camel@ht.satnam> Mime-Version: 1.0 X-Mailer: Evolution 2.24.5 (2.24.5-2.fc10) Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Currently x86_cache_size is showing partial value: L1 or L2 or L3. It should add all caches like L1 + L2 + L3 + Trace. Signed-off-by: Jaswinder Singh Rajput --- arch/x86/kernel/cpu/common.c | 2 +- arch/x86/kernel/cpu/intel_cacheinfo.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 5ce60a8..581fe17 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -422,7 +422,7 @@ void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) return; /* Again, no L2 cache is possible */ #endif - c->x86_cache_size = l2size; + c->x86_cache_size += l2size; printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", l2size, ecx & 0xFF); diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c index 789efe2..43da49e 100644 --- a/arch/x86/kernel/cpu/intel_cacheinfo.c +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c @@ -503,7 +503,7 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c) if (l3) printk(KERN_INFO "CPU: L3 cache: %dK\n", l3); - c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d)); + c->x86_cache_size = l3 + l2 + l1i + l1d + trace; return l2; } -- 1.6.0.6