From: Robert Richter <robert.richter@amd.com>
To: Peter Zijlstra <a.p.zijlstra@chello.nl>,
Stephane Eranian <eranian@googlemail.com>
Cc: Paul Mackerras <paulus@samba.org>, Ingo Molnar <mingo@elte.hu>,
LKML <linux-kernel@vger.kernel.org>,
Robert Richter <robert.richter@amd.com>
Subject: [PATCH 05/12] perf/core, x86: reduce number of CONFIG_X86_LOCAL_APIC macros
Date: Fri, 22 Jan 2010 15:22:00 +0100 [thread overview]
Message-ID: <1264170127-17402-6-git-send-email-robert.richter@amd.com> (raw)
In-Reply-To: <1264170127-17402-1-git-send-email-robert.richter@amd.com>
The function reserve_pmc_hardware() and release_pmc_hardware() were
hard to read. This patch improves readablity of the code by removing
most of the CONFIG_X86_LOCAL_APIC macros.
Signed-off-by: Robert Richter <robert.richter@amd.com>
---
arch/x86/kernel/cpu/perf_event.c | 15 +++++++++------
1 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index c49221b..5c6244b 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -711,9 +711,10 @@ again:
static atomic_t active_events;
static DEFINE_MUTEX(pmc_reserve_mutex);
+#ifdef CONFIG_X86_LOCAL_APIC
+
static bool reserve_pmc_hardware(void)
{
-#ifdef CONFIG_X86_LOCAL_APIC
int i;
if (nmi_watchdog == NMI_LOCAL_APIC)
@@ -728,11 +729,9 @@ static bool reserve_pmc_hardware(void)
if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
goto eventsel_fail;
}
-#endif
return true;
-#ifdef CONFIG_X86_LOCAL_APIC
eventsel_fail:
for (i--; i >= 0; i--)
release_evntsel_nmi(x86_pmu.eventsel + i);
@@ -747,12 +746,10 @@ perfctr_fail:
enable_lapic_nmi_watchdog();
return false;
-#endif
}
static void release_pmc_hardware(void)
{
-#ifdef CONFIG_X86_LOCAL_APIC
int i;
for (i = 0; i < x86_pmu.num_counters; i++) {
@@ -762,9 +759,15 @@ static void release_pmc_hardware(void)
if (nmi_watchdog == NMI_LOCAL_APIC)
enable_lapic_nmi_watchdog();
-#endif
}
+#else
+
+static bool reserve_pmc_hardware(void) { return true; }
+static void release_pmc_hardware(void) {}
+
+#endif
+
static inline bool bts_available(void)
{
return x86_pmu.enable_bts != NULL;
--
1.6.6
next prev parent reply other threads:[~2010-01-22 14:55 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-01-22 14:21 [PATCH 01/12] perf/core: x86 and AMD pmu updates Robert Richter
2010-01-22 14:21 ` [PATCH 01/12] perf/core: correct files in MAINTAINERS entry Robert Richter
2010-01-22 14:21 ` [PATCH 02/12] perf/core, x86: undo some some *_counter* -> *_event* renames Robert Richter
2010-01-22 14:21 ` [PATCH 03/12] perf/core, x86: remove duplicate perf_event_mask variable Robert Richter
2010-01-22 14:21 ` [PATCH 04/12] perf/core, x86: remove cpu_hw_events.interrupts Robert Richter
2010-01-22 14:22 ` Robert Richter [this message]
2010-01-22 14:22 ` [PATCH 06/12] perf/core, x86: removing p6_pmu_raw_event() Robert Richter
2010-01-22 14:22 ` [PATCH 07/12] perf/core, x86: rename macro in ARCH_PERFMON_EVENTSEL_ENABLE Robert Richter
2010-01-22 14:22 ` [PATCH 08/12] perf/core, x86: implement ARCH_PERFMON_EVENTSEL bit masks Robert Richter
2010-01-22 14:22 ` [PATCH 09/12] perf/core, x86: use test_and_set_bit() to when grabbing a counter Robert Richter
2010-01-22 14:22 ` [PATCH 10/12] perf/core, x86: removing fixed counter handling for AMD pmu Robert Richter
2010-01-22 14:22 ` [PATCH 11/12] perf/core, x86: make event_constraints a member of struct x86_pmu Robert Richter
2010-01-22 14:22 ` [PATCH 12/12] perf/core, x86: make event constraint handler generic Robert Richter
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