Re: [PATCH 4/5] x86, NMI: Allow NMI reason io port (0x61) to be processed on any CPU

Don Zickus
2010-10-20T14:27:50Z

On Wed, Oct 20, 2010 at 08:23:12AM +0800, Huang Ying wrote:
> > > > What about using raw_spin_trylock() instead? We don't have to wait
> > > > here since we are already processing it by another cpu.
> > >
> > > This would avoid a global lock and also deadlocking in case of a
> > > potential #gp in the nmi handler.
> >
> > I would feel more comfortable with it too. I can't find a reason where
> > trylock would do harm.
>
> One possible issue can be as follow:
>
> - PCI SERR NMI raised on CPU 0
> - IOCHK NMI raised on CPU 1
>
> If we use try lock, we may get unknown NMI on one CPU. Do you guys think
> so?

I thought both PCI SERR and IOCK NMI's were external and routed through
the IOAPIC, which means only one cpu could receive those (unless the
IOAPIC was updated to route them elsewhere). This would make the issue
moot. Unless I am misunderstanding where those NMIs come from?

Also as Robert said, we used to handle them on the bsp cpu only before
without any issues. I believed that was because everything in the IOAPIC
was routed that way.

I thought the point of this patch was to remove that restriction in the
nmi handler, which would allow future patches to re-route these NMIs to
another cpu, thus finally allowing people to hot-remove the bsp cpu, no?

Cheers,
Don