Re: [PATCH 4/5] x86, NMI: Allow NMI reason io port (0x61) to be processed on any CPU

Huang Ying
2010-10-21T01:25:13Z

On Thu, 2010-10-21 at 09:18 +0800, Don Zickus wrote:
> On Thu, Oct 21, 2010 at 08:40:07AM +0800, Huang Ying wrote:
> > On Wed, 2010-10-20 at 22:27 +0800, Don Zickus wrote:
> > > I thought the point of this patch was to remove that restriction in the
> > > nmi handler, which would allow future patches to re-route these NMIs to
> > > another cpu, thus finally allowing people to hot-remove the bsp cpu, no?
> >
> > Yes. We just want to make it possible to hot-remove the bsp cpu. Because
> > IOAPIC is configurable, I think it is possible to configure IOAPIC to
> > send PCI SERR NMI to one CPU while IOCK NMI to another CPU. Why not
> > support this situation too? It does not harm anything but performance to
>
> Why would we want to? It seems simpler to have one cpu dedicated to
> handling the external NMIs.

If we can guarantee that these NMIs will be only sent to one CPU, I am
fine with trylock.

> > use raw_spin_lock() instead of raw_spin_trylock() here. And for hardware
> > error processing, performance is not so important in fact.
>
> I don't know. I was always a little uncomfortable with a spin_lock there,
> so I am more supportive of a trylock.

Best Regards,
Huang Ying