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From: Peter Zijlstra <a.p.zijlstra@chello.nl>
To: Andi Kleen <andi@firstfloor.org>
Cc: eranian@google.com, linux-kernel@vger.kernel.org, x86@kernel.org,
	Andi Kleen <ak@linux.intel.com>
Subject: Re: [PATCH 3/4] perf-events: Add support for supplementary event registers v3
Date: Thu, 18 Nov 2010 13:07:36 +0100	[thread overview]
Message-ID: <1290082056.2109.1406.camel@laptop> (raw)
In-Reply-To: <1290077254-12165-4-git-send-email-andi@firstfloor.org>

On Thu, 2010-11-18 at 11:47 +0100, Andi Kleen wrote:
> From: Andi Kleen <ak@linux.intel.com>
> 
> Intel Nehalem/Westmere have a special OFFCORE_RESPONSE event
> that can be used to monitor any offcore accesses from a core.
> This is a very useful event for various tunings, and it's
> also needed to implement the generic LLC-* events correctly.
> 
> Unfortunately this event requires programming a mask in a separate
> register. And worse this separate register is per core, not per
> CPU thread.
> 
> This patch adds:
> - Teaches perf_events that OFFCORE_RESPONSE needs extra parameters.
> The extra parameters are passed by user space in the unused upper
> 32bits of the config word.
> - Add support to the Intel perf_event core to schedule per
> core resources. This adds fairly generic infrastructure that
> can be also used for other per core resources.
> The basic code has is patterned after the similar AMD northbridge
> constraints code.
> 
> Thanks to Stephane Eranian who pointed out some problems
> in the original version and suggested improvements.

WARNING: please, no space before tabs
#59: FILE: arch/x86/kernel/cpu/perf_event.c:136:
+^Iint ^I^I^I^Ipercore_used; /* Used by this CPU? */$

WARNING: please, no space before tabs
#80: FILE: arch/x86/kernel/cpu/perf_event.c:198:
+^Iu64 ^I^I^Iconfig_mask;$

WARNING: please, no space before tabs
#81: FILE: arch/x86/kernel/cpu/perf_event.c:199:
+^Iu64 ^I^I^Ivalid_mask;$

WARNING: please, no space before tabs
#85: FILE: arch/x86/kernel/cpu/perf_event.c:203:
+^I.event = (e),    ^I\$

WARNING: please, no space before tabs
#86: FILE: arch/x86/kernel/cpu/perf_event.c:204:
+^I.msr = (ms),^I     ^I\$

WARNING: please, no space before tabs
#87: FILE: arch/x86/kernel/cpu/perf_event.c:205:
+^I.config_mask = (m),  ^I\$

WARNING: please, no space before tabs
#177: FILE: arch/x86/kernel/cpu/perf_event_intel.c:12:
+^Iint ^I^Iref;^I^I/* reference count */$

WARNING: please, no space before tabs
#179: FILE: arch/x86/kernel/cpu/perf_event_intel.c:14:
+^Iu64 ^I^Iextra_config;^I/* extra MSR config */$

WARNING: please, no space before tabs
#183: FILE: arch/x86/kernel/cpu/perf_event_intel.c:18:
+^Iraw_spinlock_t ^I^Ilock;^I^I/* protect structure */$

WARNING: please, no space before tabs
#184: FILE: arch/x86/kernel/cpu/perf_event_intel.c:19:
+^Istruct er_account ^Iregs[MAX_EXTRA_REGS];$

WARNING: please use device_initcall() instead of __initcall()
#408: FILE: arch/x86/kernel/cpu/perf_event_intel.c:1108:
+__initcall(init_intel_percore);


Fixed those up, please be more careful next time.

  parent reply	other threads:[~2010-11-18 12:07 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-11-18 10:47 perf offcore patchkit for merge Andi Kleen
2010-11-18 10:47 ` [PATCH 1/4] x86: set cpu masks before calling CPU_STARTING notifiers Andi Kleen
2010-11-18 11:52   ` Thomas Gleixner
2010-11-18 13:39     ` Andi Kleen
2010-11-26 15:05   ` [tip:perf/core] x86: Set " tip-bot for Andi Kleen
2010-11-18 10:47 ` [PATCH 2/4] perf: Document enhanced event encoding for OFFCORE_MSR Andi Kleen
2010-11-18 10:47 ` [PATCH 3/4] perf-events: Add support for supplementary event registers v3 Andi Kleen
2010-11-18 11:12   ` Peter Zijlstra
2010-11-18 11:16     ` Andi Kleen
2010-11-18 11:46       ` Peter Zijlstra
2010-11-26 15:28         ` Peter Zijlstra
2010-11-26 15:30           ` Peter Zijlstra
2010-11-18 12:07   ` Peter Zijlstra [this message]
2010-11-22 12:23   ` Lin Ming
2010-11-22 12:47     ` Stephane Eranian
2010-11-22 13:01       ` Lin Ming
2010-12-01 14:27   ` Peter Zijlstra
2010-12-01 16:19     ` Peter Zijlstra
2010-11-18 10:47 ` [PATCH 4/4] perf-events: Fix LLC-* events on Intel Nehalem/Westmere v2 Andi Kleen

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