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Subject: Re: [PATCH 7/7] perf: Add load latency monitoring on Intel
 Nehalem/Westmere v2
From: Peter Zijlstra <a.p.zijlstra@chello.nl>
To: Lin Ming <ming.m.lin@intel.com>
Cc: Ingo Molnar <mingo@elte.hu>, Andi Kleen <andi@firstfloor.org>,
        Stephane Eranian <eranian@google.com>,
        lkml <linux-kernel@vger.kernel.org>
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Date: Wed, 05 Jan 2011 10:50:53 +0100
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On Mon, 2010-12-27 at 23:39 +0800, Lin Ming wrote:
> +/* Bits(0-1) {L1, L2, L3, RAM} or {unknown, IO, uncached} */
> +#define LD_LAT_L1                      0x00
> +#define LD_LAT_L2                      0x01
> +#define LD_LAT_L3                      0x02
> +#define LD_LAT_RAM                     0x03
> +#define LD_LAT_UNKNOWN                 0x00
> +#define LD_LAT_IO                      0x01
> +#define LD_LAT_UNCACHED                        0x02
> +
> +/* Bits(2-3) {not-used, snoop, local, remote} */
> +#define LD_LAT_NOT_USED                        (0x00 << 2)
> +#define LD_LAT_SNOOP                   (0x01 << 2)
> +#define LD_LAT_LOCAL                   (0x02 << 2)
> +#define LD_LAT_REMOTE                  (0x03 << 2)
> +
> +/* Bits(4-5) {modified, exclusive, shared, invalid} */
> +#define LD_LAT_MODIFIED                        (0x00 << 4)
> +#define LD_LAT_EXCLUSIVE               (0x01 << 4)
> +#define LD_LAT_SHARED                  (0x02 << 4)
> +#define LD_LAT_INVALID                 (0x03 << 4)
> +
> +#define LD_LAT_RESERVED                        0x3F


Also, I guess we need to go actually look at the POWER, IA64 and other
PMU docs to see if this sufficiently covers their data-source
capabilities.

Stephane, do you know of more PMUs with data-source capabilities we need
to include in the audit, and do you happen to have all their docs
readily available or do I need to ask google?