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Subject: Re: [PATCH 2/7] perf-events: Add support for supplementary event
 registers v4
From: Peter Zijlstra <a.p.zijlstra@chello.nl>
To: Stephane Eranian <eranian@google.com>
Cc: Lin Ming <ming.m.lin@intel.com>, Ingo Molnar <mingo@elte.hu>,
        Andi Kleen <andi@firstfloor.org>, lkml <linux-kernel@vger.kernel.org>,
        paulus <paulus@samba.org>
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Date: Thu, 13 Jan 2011 18:41:05 +0100
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On Thu, 2011-01-13 at 18:31 +0100, Stephane Eranian wrote:
> In fact, given that the Sandy Bridge PMU spec is now available, we
> have a first example of this (see Vol3b figure 30.29). OFFCORE_RESPONSE
> needs 38 bits. So, instead of having NHM/WSM use attr->config and SNB
> use another field, I think it would make sense to have that in a new u64 field
> for all processors. Despite the fact that OFFCORE_RESPONSE remains
> a model-specific feature, I think it would help user tools and libraries if we
> were to use a dedicated field. 

Paul, iirc you talked about a u64 perf_event_attr::config2 way back, are
there any ppc features that want this too?