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Wed, 17 Dec 2025 04:33:12 +0000 (GMT) From: "Alim Akhtar" To: "'Youngmin Nam'" , , , , , , Cc: , , , , , , , In-Reply-To: <20251202093613.852109-3-youngmin.nam@samsung.com> Subject: RE: [PATCH v3 2/5] pinctrl: samsung: fix incorrect pin-bank entries on Exynos2200/7885/8890/8895 Date: Wed, 17 Dec 2025 10:03:10 +0530 Message-ID: <12a401dc6f0e$441ae1f0$cc50a5d0$@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQF3wuMlGH6lOpjjwF0q/fgc3qftgQIr5xjBAatK81O1z9vLcA== Content-Language: en-us X-CMS-MailID: 20251217043317epcas5p303a51a5ecae59ec994dec8d1ae7bce9d X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20251202093027epcas2p24adbd3226dd50b2780baceee6588f3ba References: <20251202093613.852109-1-youngmin.nam@samsung.com> <20251202093613.852109-3-youngmin.nam@samsung.com> Hello Youngmin > -----Original Message----- > From: Youngmin Nam > Sent: Tuesday, December 2, 2025 3:06 PM > To: krzk=40kernel.org; s.nawrocki=40samsung.com; alim.akhtar=40samsung.co= m; > linus.walleij=40linaro.org; peter.griffin=40linaro.org; > semen.protsenko=40linaro.org; ivo.ivanov.ivanov1=40gmail.com > Cc: ryu.real=40samsung.com; d7271.choe=40samsung.com; > shin.son=40samsung.com; jaewon02.kim=40samsung.com; linux-arm- > kernel=40lists.infradead.org; linux-samsung-soc=40vger.kernel.org; linux- > gpio=40vger.kernel.org; linux-kernel=40vger.kernel.org; Youngmin Nam > > Subject: =5BPATCH v3 2/5=5D pinctrl: samsung: fix incorrect pin-bank entr= ies on > Exynos2200/7885/8890/8895 >=20 > This patch corrects wrong pin bank table definitions for 4 SoCs based on = their > TRMs. >=20 > Exynos2200 > - gpq0/1/2 were using EXYNOS_PIN_BANK_EINTN(), which implies a > 'bank_type_off' layout (.fld_width =3D =7B4,1,2,2,2,2=7D). > - Per the SoC TRM these banks must use the 'alive' layout > (.fld_width =3D =7B4,1,4,4=7D). > - Switch them to EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, ...). >=20 > Exynos7885 > - etc0, etc1: update bank type to match the SoC TRM. > - gpq0 is a non-wakeup interrupt bank; change EINTW -> EINTN accordingly. >=20 > Exynos8890 > - Per the SoC TRM, rename bank ect0 to gpb3 and mark it as > a non-external interrupt bank. > - gpi1, gpi2: update bank type to match the SoC TRM. > exynos8895_bank_type_off (.fld_width =3D =7B4,1,2,3,2,2=7D) -> > exynos5433_bank_type_off (.fld_width =3D =7B4,1,2,4,2,2=7D) > - Per the SoC TRM, mark etc1 as a non-external interrupt bank. > - apply lower case style for hex numbers. >=20 > Exynos8895 > - gpa4 is a non-wakeup interrupt bank per the SoC TRM. > change EINTW -> EINTN. (The bank_type itself was correct and is kept > unchanged.) > - apply lower case style for hex numbers. >=20 > This aligns the pin-bank tables with the documented bitfield layouts and > wakeup domains. No DT/ABI change. >=20 > Signed-off-by: Youngmin Nam > Reviewed-by: Sam Protsenko > Reviewed-by: Ivaylo Ivanov > Tested-by: Sam Protsenko > --- Reviewed-by: Alim Akhtar Tested on Exynosautov920 SADK board Tested-by: Alim Akhtar