From: Peter Zijlstra <a.p.zijlstra@chello.nl>
To: Lin Ming <ming.m.lin@intel.com>
Cc: "Ingo Molnar" <mingo@elte.hu>, "Andi Kleen" <ak@linux.intel.com>,
linux-kernel <linux-kernel@vger.kernel.org>,
"Mike Galbraith" <efault@gmx.de>,
"Arnaldo Carvalho de Melo" <acme@redhat.com>,
"Frédéric Weisbecker" <fweisbec@gmail.com>,
"Steven Rostedt" <rostedt@goodmis.org>
Subject: Re: [PATCH] perf events, x86: Implement Sandybridge last-level cache events
Date: Tue, 10 May 2011 16:29:32 +0200 [thread overview]
Message-ID: <1305037772.2914.88.camel@laptop> (raw)
In-Reply-To: <1305037078.2226.18.camel@localhost>
On Tue, 2011-05-10 at 22:17 +0800, Lin Ming wrote:
>
> I'm also not sure if the bits combination do count exactly
> L3_HIT/_MISS.
>
<snip manual bits>
> May need some micro-benchmarks to verify it.
either that or ask for clarification internally.
next prev parent reply other threads:[~2011-05-10 14:47 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-05-09 8:39 [PATCH] perf events, x86: Implement Sandybridge last-level cache events Lin Ming
2011-05-10 10:08 ` Peter Zijlstra
2011-05-10 14:17 ` Lin Ming
2011-05-10 14:29 ` Peter Zijlstra [this message]
2011-05-10 15:29 ` Ingo Molnar
-- strict thread matches above, loose matches on Subject: below --
2011-05-06 7:14 [PATCH] perf events, x86: Add SandyBridge stalled-cycles-frontend/backend events Lin Ming
2011-05-06 7:38 ` Ingo Molnar
2011-05-06 9:19 ` [PATCH] perf events, x86: Implement Sandybridge last-level cache events Ingo Molnar
2011-05-06 13:47 ` Lin Ming
2011-05-09 8:45 ` Lin Ming
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