From: Peter Zijlstra <peterz@infradead.org>
To: Stephane Eranian <eranian@google.com>
Cc: linux-kernel@vger.kernel.org, mingo@elte.hu, andi@firstfloor.org,
ming.m.lin@intel.com
Subject: Re: [PATCH 0/3] perf_events: update extra shared registers management (v2)
Date: Mon, 23 May 2011 11:32:48 +0200 [thread overview]
Message-ID: <1306143168.18455.10.camel@twins> (raw)
In-Reply-To: <1306141897.18455.8.camel@twins>
On Mon, 2011-05-23 at 11:11 +0200, Peter Zijlstra wrote:
> + if (event->hw.extra_reg.idx == EXTRA_REG_RSP_0) {
> + event->attr.config = 0x01bb;
> + event->hw.extra_reg.idx = EXTRA_REG_RSP_1;
> + event->hw.extra_reg.msr = MSR_OFFCORE_RSP_1;
> + } else if (event->hw.extra_reg.idx == EXTRA_REG_RSP_1) {
> + event->attr.config = 0x01b7;
> + event->hw.extra_reg.idx = EXTRA_REG_RSP_0;
> + event->hw.extra_reg.msr = MSR_OFFCORE_RSP_0;
> + }
clearly I meant to write:
event->hw.config &= ~X86_RAW_EVENT_MASK;
event->hw.config |= 0x01b[b7];
:-)
next prev parent reply other threads:[~2011-05-23 9:33 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-05-20 14:37 [PATCH 0/3] perf_events: update extra shared registers management (v2) Stephane Eranian
2011-05-23 9:11 ` Peter Zijlstra
2011-05-23 9:32 ` Peter Zijlstra [this message]
2011-05-23 9:36 ` Stephane Eranian
2011-05-23 10:58 ` Stephane Eranian
2011-05-23 11:10 ` Peter Zijlstra
2011-05-23 12:00 ` Stephane Eranian
2011-05-23 15:15 ` Peter Zijlstra
2011-05-23 15:27 ` Stephane Eranian
2011-05-23 15:30 ` Peter Zijlstra
2011-05-23 11:11 ` Peter Zijlstra
2011-05-23 11:56 ` Stephane Eranian
2011-05-23 15:15 ` Peter Zijlstra
2011-07-01 15:23 ` [tip:perf/core] perf, intel: Try alternative OFFCORE encodings tip-bot for Peter Zijlstra
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