From: Peter Zijlstra <peterz@infradead.org>
To: Stephane Eranian <eranian@google.com>
Cc: LKML <linux-kernel@vger.kernel.org>,
"mingo@elte.hu" <mingo@elte.hu>, Andi Kleen <andi@firstfloor.org>,
Lin Ming <ming.m.lin@intel.com>
Subject: Re: [PATCH 0/3] perf_events: update extra shared registers management (v2)
Date: Mon, 23 May 2011 13:11:48 +0200 [thread overview]
Message-ID: <1306149108.18455.13.camel@twins> (raw)
In-Reply-To: <BANLkTinN92UpxU85r17zB+Khba8k59nJTA@mail.gmail.com>
On Mon, 2011-05-23 at 12:58 +0200, Stephane Eranian wrote:
> >> event->hw.config &= ~X86_RAW_EVENT_MASK;
>
> Not quite, you want INTEL_ARCH_EVENT_MASK instead
> because you only want to modify umask+event code.
Do EDGE,INV,CMASK actually make a difference for the OFFCORE event?
next prev parent reply other threads:[~2011-05-23 11:12 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-05-20 14:37 [PATCH 0/3] perf_events: update extra shared registers management (v2) Stephane Eranian
2011-05-23 9:11 ` Peter Zijlstra
2011-05-23 9:32 ` Peter Zijlstra
2011-05-23 9:36 ` Stephane Eranian
2011-05-23 10:58 ` Stephane Eranian
2011-05-23 11:10 ` Peter Zijlstra
2011-05-23 12:00 ` Stephane Eranian
2011-05-23 15:15 ` Peter Zijlstra
2011-05-23 15:27 ` Stephane Eranian
2011-05-23 15:30 ` Peter Zijlstra
2011-05-23 11:11 ` Peter Zijlstra [this message]
2011-05-23 11:56 ` Stephane Eranian
2011-05-23 15:15 ` Peter Zijlstra
2011-07-01 15:23 ` [tip:perf/core] perf, intel: Try alternative OFFCORE encodings tip-bot for Peter Zijlstra
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