Re: [PATCH] perf: removed a non-existent event "L1-icache-prefetches" for AMD processors

[Peter Zijlstra <a.p.zijlstra@chello.nl>]

On Mon, 2011-06-27 at 14:58 -0700, Zhengyu He wrote:
> According to AMD's "BIOS and Kernel Developer's Guide for AMD NPT Family
> 0Fh Processors"
> (http://support.amd.com/us/Processor_TechDocs/32559.pdf), 0x4B is for
> prefetch instructions dispatched, and 0x14B is for the load prefetch
> instructions including Pretech and PrefetchT0/T1/T2. No event for the
> instructions preteched into L1I cache is found.
> 
> Signed-off-by: Zhengyu He <zhengyuh@google.com>

Hmm, indeed, its prefetch instructions issues, but not instruction
prefetches, Robert, Andre agreed?

> ---
>  arch/x86/kernel/cpu/perf_event_amd.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c
> index fe29c1d..3b7f21d 100644
> --- a/arch/x86/kernel/cpu/perf_event_amd.c
> +++ b/arch/x86/kernel/cpu/perf_event_amd.c
> @@ -29,7 +29,7 @@ static __initconst const u64 amd_hw_cache_event_ids
>  		[ C(RESULT_MISS)   ] = -1,
>  	},
>  	[ C(OP_PREFETCH) ] = {
> -		[ C(RESULT_ACCESS) ] = 0x014B, /* Prefetch Instructions :Load */
> +		[ C(RESULT_ACCESS) ] = 0,
>  		[ C(RESULT_MISS)   ] = 0,
>  	},
>   },