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Subject: Re: [PATCH 1/4] perf: Add memory load/store events generic code
From: Peter Zijlstra <a.p.zijlstra@chello.nl>
To: Lin Ming <ming.m.lin@intel.com>
Cc: Ingo Molnar <mingo@elte.hu>, Andi Kleen <andi@firstfloor.org>,
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Date: Mon, 04 Jul 2011 13:16:32 +0200
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On Mon, 2011-07-04 at 08:02 +0000, Lin Ming wrote:
> +#define MEM_STORE_DCU_HIT              (1ULL << 0)

I'm pretty sure that's not Dublin City University, but what is it?
Data-Cache-Unit? what does that mean, L1/L2 or also L3? 

> +#define MEM_STORE_STLB_HIT             (1ULL << 1)

What's an sTLB? I know iTLB and dTLB's but sTLBs I've not heard of yet.

> +#define MEM_STORE_LOCKED_ACCESS                (1ULL << 2) 

Presumably that's about LOCK'ed ops?

So now you're just tacking bits on the end without even attempting to
generalize/unify things, not charmed at all.