From: Peter Zijlstra <peterz@infradead.org>
To: Robert Richter <robert.richter@amd.com>
Cc: Ingo Molnar <mingo@elte.hu>,
Arnaldo Carvalho de Melo <acme@redhat.com>,
LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 4/7] perf, x86: Implement IBS interrupt handler
Date: Fri, 29 Jul 2011 18:58:46 +0200 [thread overview]
Message-ID: <1311958726.5890.411.camel@twins> (raw)
In-Reply-To: <1311860812-28748-5-git-send-email-robert.richter@amd.com>
On Thu, 2011-07-28 at 15:46 +0200, Robert Richter wrote:
> +static int __kprobes
> +perf_ibs_nmi_handler(struct notifier_block *self,
> + unsigned long cmd, void *__args)
> +{
> + struct die_args *args = __args;
> + int handled = 0;
> +
> + switch (cmd) {
> + case DIE_NMI:
> + break;
> + default:
> + return NOTIFY_DONE;
> + }
> +
> + handled += perf_ibs_handle_irq(&perf_ibs_fetch, args->regs);
> + handled += perf_ibs_handle_irq(&perf_ibs_op, args->regs);
> +
> + if (!handled)
> + return NOTIFY_DONE;
> +
> + inc_irq_stat(apic_perf_irqs);
> +
> + return NOTIFY_STOP;
> +}
So IBS cannot trigger the whole unknown NMI business? Wouldn't ibs_op
triggering while ibs_fetch just started latch the NMI line, the
in-progress NMI would handle both, and we then end up with a spare NMI?
next prev parent reply other threads:[~2011-07-29 16:59 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-07-28 13:46 [PATCH 0/7] perf, x86: Implement AMD IBS Robert Richter
2011-07-28 13:46 ` [PATCH 1/7] perf, x86: share IBS macros between perf and oprofile Robert Richter
2011-07-28 13:46 ` [PATCH 2/7] perf, x86: Implement IBS initialization Robert Richter
2011-07-29 16:58 ` Peter Zijlstra
2011-08-01 5:27 ` Robert Richter
2011-08-02 11:49 ` Peter Zijlstra
2011-08-12 17:49 ` Robert Richter
2011-07-28 13:46 ` [PATCH 3/7] perf, x86: Implement IBS event configuration Robert Richter
2011-08-02 11:35 ` Peter Zijlstra
2011-08-12 19:51 ` Robert Richter
2011-07-28 13:46 ` [PATCH 4/7] perf, x86: Implement IBS interrupt handler Robert Richter
2011-07-29 16:58 ` Peter Zijlstra [this message]
2011-08-01 5:32 ` Robert Richter
2011-08-01 15:21 ` Peter Zijlstra
2011-08-01 16:38 ` Don Zickus
2011-08-05 9:55 ` Ingo Molnar
2011-08-05 13:47 ` Don Zickus
2011-08-02 11:43 ` Peter Zijlstra
2011-08-12 18:07 ` Robert Richter
2011-07-28 13:46 ` [PATCH 5/7] perf, x86: Implement IBS pmu control ops Robert Richter
2011-07-28 13:46 ` [PATCH 6/7] perf, x86: Example code for AMD IBS Robert Richter
2011-07-29 16:58 ` Peter Zijlstra
2011-08-01 5:50 ` Robert Richter
2011-08-02 10:37 ` Peter Zijlstra
2011-08-03 8:27 ` Michael Cree
2011-08-03 17:56 ` Robert Richter
2011-07-28 13:46 ` [PATCH 7/7] perf, x86: Implement 64 bit counter support for IBS Robert Richter
2011-07-29 16:58 ` Peter Zijlstra
2011-07-29 17:02 ` Peter Zijlstra
2011-08-01 5:55 ` Robert Richter
2011-07-29 17:01 ` Peter Zijlstra
2011-08-01 6:13 ` Robert Richter
2011-08-02 11:37 ` Peter Zijlstra
2011-08-12 18:11 ` Robert Richter
2011-07-29 17:07 ` [PATCH 0/7] perf, x86: Implement AMD IBS Peter Zijlstra
2011-08-01 5:21 ` Robert Richter
2011-08-02 11:29 ` Peter Zijlstra
2011-08-12 19:43 ` Robert Richter
2011-08-16 21:05 ` Robert Richter
-- strict thread matches above, loose matches on Subject: below --
2011-09-07 16:36 [PATCH 0/7 -v2] " Robert Richter
2011-09-07 16:36 ` [PATCH 4/7] perf, x86: Implement IBS interrupt handler Robert Richter
2011-09-14 16:13 ` Peter Zijlstra
2011-09-21 8:39 ` Robert Richter
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