Re: [PATCH 2/7] perf, x86: Implement IBS initialization

[Peter Zijlstra <peterz@infradead.org>]

On Thu, 2011-07-28 at 15:46 +0200, Robert Richter wrote:
> +/*
> + * This runs only on the current cpu. We try to find an LVT offset and
> + * setup the local APIC. For this we must disable preemption. On
> + * success we initialize all nodes with this offset. This updates then
> + * the offset in the IBS_CTL per-node msr. The per-core APIC setup of
> + * the IBS interrupt vector is handled by perf_ibs_cpu_notifier that
> + * is using the new offset.
> + */
> +static int force_ibs_eilvt_setup(void)
> +{
> +       int offset;
> +       int ret;
> +
> +       preempt_disable();
> +       /* find the next free available EILVT entry, skip offset 0 */
> +       for (offset = 1; offset < APIC_EILVT_NR_MAX; offset++) {
> +               if (get_eilvt(offset))
> +                       break;
> +       }
> +       preempt_enable();
> +
> +       if (offset == APIC_EILVT_NR_MAX) {
> +               printk(KERN_DEBUG "No EILVT entry available\n");
> +               return -EBUSY;
> +       }
> +
> +       ret = setup_ibs_ctl(offset);
> +       if (ret)
> +               goto out;
> +
> +       if (!ibs_eilvt_valid()) {
> +               ret = -EFAULT;
> +               goto out;
> +       }
> +
> +       pr_err(FW_BUG "using offset %d for IBS interrupts\n", offset);
> +       pr_err(FW_BUG "workaround enabled for IBS LVT offset\n");
> +
> +       return 0;
> +out:
> +       preempt_disable();
> +       put_eilvt(offset);
> +       preempt_enable();
> +       return ret;
> +} 

So I don't get any of that preempt_disable/enable crap in this patch,
but the above is esp. confusing. How is that preempt_disable() at out:
still valid? We could be running on an entirely different cpu from when
we did get_eilvt at the start.