From: Peter Zijlstra <peterz@infradead.org>
To: Robert Richter <robert.richter@amd.com>
Cc: Ingo Molnar <mingo@elte.hu>,
Stephane Eranian <eranian@google.com>,
LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 3/7] perf, x86: Implement IBS event configuration
Date: Wed, 14 Sep 2011 17:35:32 +0200 [thread overview]
Message-ID: <1316014532.5040.26.camel@twins> (raw)
In-Reply-To: <1315413376-769-4-git-send-email-robert.richter@amd.com>
On Wed, 2011-09-07 at 18:36 +0200, Robert Richter wrote:
> +static struct perf_ibs perf_ibs_fetch = {
> + .pmu = {
> + .event_init = perf_ibs_init,
> + .add = perf_ibs_add,
> + .del = perf_ibs_del,
> + },
> + .msr = MSR_AMD64_IBSFETCHCTL,
> + .config_mask = IBS_FETCH_CONFIG_MASK,
> + .cnt_mask = IBS_FETCH_MAX_CNT,
> + .enable_mask = IBS_FETCH_ENABLE,
> +};
> +
> +static struct perf_ibs perf_ibs_op = {
> + .pmu = {
> + .event_init = perf_ibs_init,
> + .add = perf_ibs_add,
> + .del = perf_ibs_del,
> + },
> + .msr = MSR_AMD64_IBSOPCTL,
> + .config_mask = IBS_OP_CONFIG_MASK,
> + .cnt_mask = IBS_OP_MAX_CNT,
> + .enable_mask = IBS_OP_ENABLE,
> };
Both those .pmu things want:
.task_ctx_nr = perf_invalid_context,
disabling per-task events, or you need to create a new context and
somehow fix per-task scheduling for these two things.
Adding two task contexts (one for each type) really isn't nice.
next prev parent reply other threads:[~2011-09-14 15:35 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-09-07 16:36 [PATCH 0/7 -v2] perf, x86: Implement AMD IBS Robert Richter
2011-09-07 16:36 ` [PATCH 1/7] perf, x86: share IBS macros between perf and oprofile Robert Richter
2011-09-07 16:36 ` [PATCH 2/7] perf, x86: Implement IBS initialization Robert Richter
2011-09-07 16:36 ` [PATCH 3/7] perf, x86: Implement IBS event configuration Robert Richter
2011-09-14 15:35 ` Peter Zijlstra [this message]
2011-09-07 16:36 ` [PATCH 4/7] perf, x86: Implement IBS interrupt handler Robert Richter
2011-09-14 16:13 ` Peter Zijlstra
2011-09-21 8:39 ` Robert Richter
2011-09-07 16:36 ` [PATCH 5/7] perf, x86: Implement IBS pmu control ops Robert Richter
2011-09-07 16:36 ` [PATCH 6/7] perf, x86: Implement 64 bit counter support for IBS Robert Richter
2011-09-07 16:36 ` [PATCH 7/7] perf, x86: Example code for AMD IBS Robert Richter
-- strict thread matches above, loose matches on Subject: below --
2011-07-28 13:46 [PATCH 0/7] perf, x86: Implement " Robert Richter
2011-07-28 13:46 ` [PATCH 3/7] perf, x86: Implement IBS event configuration Robert Richter
2011-08-02 11:35 ` Peter Zijlstra
2011-08-12 19:51 ` Robert Richter
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