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Subject: Re: [Patch] Idle balancer: cache align nohz structure to improve
 idle load balancing scalability
From: Suresh Siddha <suresh.b.siddha@intel.com>
Reply-To: Suresh Siddha <suresh.b.siddha@intel.com>
To: Eric Dumazet <eric.dumazet@gmail.com>
Cc: Tim Chen <tim.c.chen@linux.intel.com>, Ingo Molnar <mingo@elte.hu>,
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Organization: Intel
Date: Wed, 19 Oct 2011 22:57:44 -0700
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On Wed, 2011-10-19 at 21:18 -0700, Eric Dumazet wrote:
> > +	atomic_t load_balancer ____cacheline_aligned;
> > +	atomic_t first_pick_cpu ____cacheline_aligned;
> > +	atomic_t second_pick_cpu ____cacheline_aligned;
> > +	cpumask_var_t idle_cpus_mask ____cacheline_aligned;
> >  	cpumask_var_t grp_idle_mask;
> >  	unsigned long next_balance;     /* in jiffy units */
> >  } nohz ____cacheline_aligned;
> > 
> 
> Dont you increase cache footprint, say for an Uniprocessor machine ?
> 
> (CONFIG_SMP=n)
> 
> ____cacheline_aligned_in_smp seems more suitable in this case.

I believe this code is already under ifdef CONFIG_SMP.

thanks,
suresh