Re: [RFC][PATCH 3/3] x86: Add workaround to NMI iret woes

[Steven Rostedt <rostedt@goodmis.org>]

On Fri, 2011-12-09 at 18:49 +0100, Borislav Petkov wrote:
> Hey Steve,
> 
> On Fri, Dec 09, 2011 at 12:19:31PM -0500, Steven Rostedt wrote:
> > Could you shed some light on this. Can an NMI interrupt an MCE in
> > progress?
> 
> Easy, http://support.amd.com/us/Processor_TechDocs/APM_V2_24593.pdf,
> section 8.5.
> 
> On amd64 #MC is along with processor reset the highest prio. Judging
> from the text, an NMI occurring during an #MC is held until we return
> from the #MC handler:
> 
> "When simultaneous interrupts occur, the processor transfers control
> to the highest-priority interrupt handler. Lower-priority interrupts
> from external sources are held pending by the processor, and they are
> handled after the higher-priority interrupt is handled. Lower-priority
> interrupts that result from internal sources are discarded. Those
> interrupts reoccur when the high-priority interrupt handler completes
> and transfers control back to the interrupted instruction."

Yeah, I read that too. It's just a little confusing because how the SMI
section talks about disabling NMIs, but nothing else does. And according
to that same table, SMIs are higher priority. So why mention that it
disables NMIs?

Ah, looking at that section again, I see:

"SMM is entered using the system-management interrupt (SMI).
SMI is an external non-maskable interrupt that operates
differently from and independently of other interrupts. SMI has
priority over all other external interrupts, including NMI (see
“Priorities” on page 269 for a list of the interrupt priorities)."

That 'See "Priorities" on page 269' help verify that this is indeed the
case.

Thanks!

-- Steve