[PATCH 0/4] perf_events: add support for Intel reference cycles event

[PATCH 0/4] perf_events: add support for Intel reference cycles event

[Stephane Eranian]

The unhalted_reference_cycles is a very useful event which counts cycles at the
reference CPU clock speed (same as TSC if processors supports constant_tsc).
That means, it keeps a constant correlation with wall-clock time while the
processor is not halted, unlike its counter-part unhalted_core_cycles.
The latter event, used by generic PMU event cycles in the perf tool is
subject to frequency down-scaling AND Turbo mode fluctuations.

The unhlated_reference_cycles is NOT equivalent to wall clock time because
it counts only when the processor is not in halted state. But this limitation
impacts only system-wide measurements.

The unhalted_reference_cycles can only be counted on fixed counter 2.
As such, it does not have an event encoding. Fixed counters can only measure
one (hardwired) event. Yet, with perf_events user manipulates events and not
counters, thus each event needs an encoding. That encoding is then used by
the kernel to identify the event and schedule it on the proper counter.

Up until now, there was no encoding chosen for unhalted_reference_cycles, thus
it could not be scheduled properly and thus it was not supported.

This patch uses the encoding 0x0300. That means event code 0x00, umask 0x3.
That event code is not used by Intel on any existing processor. We have
also checked with Intel and it seems that they don't plan on using it in
the future.

With this patch, it is possible to see the effect of Turbo mode:

$ perf stat -e unhalted_reference_cycles,unhalted_core_cycles ./noploop 1
noploop for 1 seconds

Performance counter stats for './noploop 1':

3,197,640,960 unhalted_reference_cycles
3,595,043,997 unhalted_core_cycles

1.000732233  seconds time elapsed

Signed-off-by: Stephane Eranian <eranian@google.com>
---

Stephane Eranian (4):
  perf_events: enable raw event support for Intel
    unhalted_reference_cycles event
  perf_event: add PERF_COUNT_HW_REF_CPU_CYCLES generic PMU event
  perf_events: add Intel X86 mapping for PERF_COUNT_HW_REF_CPU_CYCLES
  perf: add support for PERF_HW_COUNT_REF_CPU_CYCLES

 arch/x86/include/asm/perf_event.h      |   15 ++++++++-------
 arch/x86/kernel/cpu/perf_event.c       |    8 +++++++-
 arch/x86/kernel/cpu/perf_event_intel.c |   16 ++++++----------
 include/linux/perf_event.h             |    1 +
 tools/perf/util/parse-events.c         |    2 ++
 5 files changed, 24 insertions(+), 18 deletions(-)

[PATCH 1/4] perf_events: enable raw event support for Intel unhalted_reference_cycles event

[Stephane Eranian]

This patch adds the encoding and definitions necessary for the
unhalted_reference_cycles event avaialble since Intel Core 2 processors.

Signed-off-by: Stephane Eranian <eranian@google.com>
---
 arch/x86/include/asm/perf_event.h      |   15 ++++++++-------
 arch/x86/kernel/cpu/perf_event.c       |    8 +++++++-
 arch/x86/kernel/cpu/perf_event_intel.c |   15 +++++----------
 3 files changed, 20 insertions(+), 18 deletions(-)

diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index b50e9d1..096c975 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -112,23 +112,24 @@ struct x86_pmu_capability {
 /*
  * All 3 fixed-mode PMCs are configured via this single MSR:
  */
-#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL			0x38d
+#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL	0x38d
 
 /*
  * The counts are available in three separate MSRs:
  */
 
 /* Instr_Retired.Any: */
-#define MSR_ARCH_PERFMON_FIXED_CTR0			0x309
-#define X86_PMC_IDX_FIXED_INSTRUCTIONS			(X86_PMC_IDX_FIXED + 0)
+#define MSR_ARCH_PERFMON_FIXED_CTR0	0x309
+#define X86_PMC_IDX_FIXED_INSTRUCTIONS	(X86_PMC_IDX_FIXED + 0)
 
 /* CPU_CLK_Unhalted.Core: */
-#define MSR_ARCH_PERFMON_FIXED_CTR1			0x30a
-#define X86_PMC_IDX_FIXED_CPU_CYCLES			(X86_PMC_IDX_FIXED + 1)
+#define MSR_ARCH_PERFMON_FIXED_CTR1	0x30a
+#define X86_PMC_IDX_FIXED_CPU_CYCLES	(X86_PMC_IDX_FIXED + 1)
 
 /* CPU_CLK_Unhalted.Ref: */
-#define MSR_ARCH_PERFMON_FIXED_CTR2			0x30b
-#define X86_PMC_IDX_FIXED_BUS_CYCLES			(X86_PMC_IDX_FIXED + 2)
+#define MSR_ARCH_PERFMON_FIXED_CTR2	0x30b
+#define X86_PMC_IDX_FIXED_REF_CYCLES	(X86_PMC_IDX_FIXED + 2)
+#define X86_PMC_MSK_FIXED_REF_CYCLES	(1ULL << X86_PMC_IDX_FIXED_REF_CYCLES)
 
 /*
  * We model BTS tracing as another fixed-mode PMC.
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index 930fe48..5adce10 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -1304,9 +1304,15 @@ static int __init init_hw_perf_events(void)
 				   0, x86_pmu.num_counters, 0);
 
 	if (x86_pmu.event_constraints) {
+		/*
+		 * event on fixed counter2 (REF_CYCLES) only works on this
+		 * counter, so do not extend mask to generic counters
+		 */
 		for_each_event_constraint(c, x86_pmu.event_constraints) {
-			if (c->cmask != X86_RAW_EVENT_MASK)
+			if (c->cmask != X86_RAW_EVENT_MASK
+			    || c->idxmsk64 == X86_PMC_MSK_FIXED_REF_CYCLES) {
 				continue;
+			}
 
 			c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
 			c->weight += x86_pmu.num_counters;
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 2c3bf53..61f865f 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -45,12 +45,7 @@ static struct event_constraint intel_core2_event_constraints[] __read_mostly =
 {
 	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
-	/*
-	 * Core2 has Fixed Counter 2 listed as CPU_CLK_UNHALTED.REF and event
-	 * 0x013c as CPU_CLK_UNHALTED.BUS and specifies there is a fixed
-	 * ratio between these counters.
-	 */
-	/* FIXED_EVENT_CONSTRAINT(0x013c, 2),  CPU_CLK_UNHALTED.REF */
+	FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 	INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
 	INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
 	INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
@@ -68,7 +63,7 @@ static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
 {
 	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
-	/* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
+	FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 	INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
 	INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
 	INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
@@ -90,7 +85,7 @@ static struct event_constraint intel_westmere_event_constraints[] __read_mostly 
 {
 	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
-	/* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
+	FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 	INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
 	INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
 	INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
@@ -102,7 +97,7 @@ static struct event_constraint intel_snb_event_constraints[] __read_mostly =
 {
 	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
-	/* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
+	FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 	INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
 	INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
 	INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
@@ -125,7 +120,7 @@ static struct event_constraint intel_gen_event_constraints[] __read_mostly =
 {
 	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
-	/* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
+	FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 	EVENT_CONSTRAINT_END
 };
 
-- 
1.7.1

[tip:perf/core] perf events: Enable raw event support for Intel unhalted_reference_cycles event

[tip-bot for Stephane Eranian]

Commit-ID:  cd09c0c40a971549800ce6a7e53c63f5139dd175
Gitweb:     http://git.kernel.org/tip/cd09c0c40a971549800ce6a7e53c63f5139dd175
Author:     Stephane Eranian <eranian@google.com>
AuthorDate: Sun, 11 Dec 2011 00:28:51 +0100
Committer:  Ingo Molnar <mingo@elte.hu>
CommitDate: Wed, 21 Dec 2011 10:26:32 +0100

perf events: Enable raw event support for Intel unhalted_reference_cycles event

This patch adds the encoding and definitions necessary for the
unhalted_reference_cycles event avaialble since Intel Core 2 processors.

Signed-off-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/1323559734-3488-2-git-send-email-eranian@google.com
Signed-off-by: Ingo Molnar <mingo@elte.hu>
---
 arch/x86/include/asm/perf_event.h      |   15 ++++++++-------
 arch/x86/kernel/cpu/perf_event.c       |    8 +++++++-
 arch/x86/kernel/cpu/perf_event_intel.c |   15 +++++----------
 3 files changed, 20 insertions(+), 18 deletions(-)

diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index b50e9d1..096c975 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -112,23 +112,24 @@ struct x86_pmu_capability {
 /*
  * All 3 fixed-mode PMCs are configured via this single MSR:
  */
-#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL			0x38d
+#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL	0x38d
 
 /*
  * The counts are available in three separate MSRs:
  */
 
 /* Instr_Retired.Any: */
-#define MSR_ARCH_PERFMON_FIXED_CTR0			0x309
-#define X86_PMC_IDX_FIXED_INSTRUCTIONS			(X86_PMC_IDX_FIXED + 0)
+#define MSR_ARCH_PERFMON_FIXED_CTR0	0x309
+#define X86_PMC_IDX_FIXED_INSTRUCTIONS	(X86_PMC_IDX_FIXED + 0)
 
 /* CPU_CLK_Unhalted.Core: */
-#define MSR_ARCH_PERFMON_FIXED_CTR1			0x30a
-#define X86_PMC_IDX_FIXED_CPU_CYCLES			(X86_PMC_IDX_FIXED + 1)
+#define MSR_ARCH_PERFMON_FIXED_CTR1	0x30a
+#define X86_PMC_IDX_FIXED_CPU_CYCLES	(X86_PMC_IDX_FIXED + 1)
 
 /* CPU_CLK_Unhalted.Ref: */
-#define MSR_ARCH_PERFMON_FIXED_CTR2			0x30b
-#define X86_PMC_IDX_FIXED_BUS_CYCLES			(X86_PMC_IDX_FIXED + 2)
+#define MSR_ARCH_PERFMON_FIXED_CTR2	0x30b
+#define X86_PMC_IDX_FIXED_REF_CYCLES	(X86_PMC_IDX_FIXED + 2)
+#define X86_PMC_MSK_FIXED_REF_CYCLES	(1ULL << X86_PMC_IDX_FIXED_REF_CYCLES)
 
 /*
  * We model BTS tracing as another fixed-mode PMC.
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index 930fe48..5adce10 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -1304,9 +1304,15 @@ static int __init init_hw_perf_events(void)
 				   0, x86_pmu.num_counters, 0);
 
 	if (x86_pmu.event_constraints) {
+		/*
+		 * event on fixed counter2 (REF_CYCLES) only works on this
+		 * counter, so do not extend mask to generic counters
+		 */
 		for_each_event_constraint(c, x86_pmu.event_constraints) {
-			if (c->cmask != X86_RAW_EVENT_MASK)
+			if (c->cmask != X86_RAW_EVENT_MASK
+			    || c->idxmsk64 == X86_PMC_MSK_FIXED_REF_CYCLES) {
 				continue;
+			}
 
 			c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
 			c->weight += x86_pmu.num_counters;
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 2c3bf53..61f865f 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -45,12 +45,7 @@ static struct event_constraint intel_core2_event_constraints[] __read_mostly =
 {
 	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
-	/*
-	 * Core2 has Fixed Counter 2 listed as CPU_CLK_UNHALTED.REF and event
-	 * 0x013c as CPU_CLK_UNHALTED.BUS and specifies there is a fixed
-	 * ratio between these counters.
-	 */
-	/* FIXED_EVENT_CONSTRAINT(0x013c, 2),  CPU_CLK_UNHALTED.REF */
+	FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 	INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
 	INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
 	INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
@@ -68,7 +63,7 @@ static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
 {
 	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
-	/* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
+	FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 	INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
 	INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
 	INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
@@ -90,7 +85,7 @@ static struct event_constraint intel_westmere_event_constraints[] __read_mostly
 {
 	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
-	/* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
+	FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 	INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
 	INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
 	INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
@@ -102,7 +97,7 @@ static struct event_constraint intel_snb_event_constraints[] __read_mostly =
 {
 	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
-	/* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
+	FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 	INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
 	INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
 	INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
@@ -125,7 +120,7 @@ static struct event_constraint intel_gen_event_constraints[] __read_mostly =
 {
 	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
-	/* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
+	FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 	EVENT_CONSTRAINT_END
 };
 

[PATCH 2/4] perf_event: add PERF_COUNT_HW_REF_CPU_CYCLES generic PMU event

[Stephane Eranian]

This event counts the number of reference core cpu cycles.
Reference means that the event increments at a constant rate which
is not subject to core CPU frequency adjustments. The event may
not count when the processor is in halted (low power) state.
As such, it may not be equivalent to wall clock time. However,
when the processor is not halted state, the event keeps
a constant correlation with wall clock time.

Signed-off-by: Stephane Eranian <eranian@google.com>
---
 include/linux/perf_event.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index 564769c..0885561 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -54,6 +54,7 @@ enum perf_hw_id {
 	PERF_COUNT_HW_BUS_CYCLES		= 6,
 	PERF_COUNT_HW_STALLED_CYCLES_FRONTEND	= 7,
 	PERF_COUNT_HW_STALLED_CYCLES_BACKEND	= 8,
+	PERF_COUNT_HW_REF_CPU_CYCLES		= 9,
 
 	PERF_COUNT_HW_MAX,			/* non-ABI */
 };
-- 
1.7.1

Re: [PATCH 2/4] perf_event: add PERF_COUNT_HW_REF_CPU_CYCLES generic PMU event

[Ingo Molnar]

* Stephane Eranian <eranian@google.com> wrote:

> This event counts the number of reference core cpu cycles. 
> Reference means that the event increments at a constant rate 
> which is not subject to core CPU frequency adjustments. The 
> event may not count when the processor is in halted (low 
> power) state. As such, it may not be equivalent to wall clock 
> time. However, when the processor is not halted state, the 
> event keeps a constant correlation with wall clock time.
> 
> Signed-off-by: Stephane Eranian <eranian@google.com>
> ---
>  include/linux/perf_event.h |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
> index 564769c..0885561 100644
> --- a/include/linux/perf_event.h
> +++ b/include/linux/perf_event.h
> @@ -54,6 +54,7 @@ enum perf_hw_id {
>  	PERF_COUNT_HW_BUS_CYCLES		= 6,
>  	PERF_COUNT_HW_STALLED_CYCLES_FRONTEND	= 7,
>  	PERF_COUNT_HW_STALLED_CYCLES_BACKEND	= 8,
> +	PERF_COUNT_HW_REF_CPU_CYCLES		= 9,

Btw., that was what 'bus cycles' tried to do a long time ago: 
the constant, non-variable baseline heartbeat of the system.

We could simply rename that, fix the event tables where needed, 
and keep the ABI.

Just a small detail: how about naming it 'constant [frequency] 
CPU cycles'? That's a concept that might be present on other 
platforms as well.

CONST_FREQ_CYCLES or so. The 'CPU' can be dropped as well 
because it's not really the CPU's frequency anymore.

Thanks,

	Ingo

Re: [PATCH 2/4] perf_event: add PERF_COUNT_HW_REF_CPU_CYCLES generic PMU event

[Peter Zijlstra]

On Sun, 2011-12-11 at 09:01 +0100, Ingo Molnar wrote:
> > +     PERF_COUNT_HW_REF_CPU_CYCLES            = 9,
> 
> Btw., that was what 'bus cycles' tried to do a long time ago: 
> the constant, non-variable baseline heartbeat of the system. 

This isn't about that. Its about exposing the third fixed purpose
counter. Intel, in their infinite wisdom, created a fixed purpose
counter for which there is no equivalent in the general purpose events.

Our fixed purpose counter support is predicated on the assumption that
there is, and simply maps any event code to also include the fixed
purpose counter if appropriate.

There not being an event to map from has thus far avoided exposing this
third fixed purpose event.

The problem with remapping BUS_CYCLES is that BUS_CYCLES (now) is
something you can program on the {2,4,8} general purpose counters,
whereas this new thing can only ever be ran from the 1 fixed purpose
counter.

Re: [PATCH 2/4] perf_event: add PERF_COUNT_HW_REF_CPU_CYCLES generic PMU event

[Ingo Molnar]

* Peter Zijlstra <peterz@infradead.org> wrote:

> On Sun, 2011-12-11 at 09:01 +0100, Ingo Molnar wrote:
> > > +     PERF_COUNT_HW_REF_CPU_CYCLES            = 9,
> > 
> > Btw., that was what 'bus cycles' tried to do a long time ago: 
> > the constant, non-variable baseline heartbeat of the system. 
> 
> This isn't about that. Its about exposing the third fixed 
> purpose counter. Intel, in their infinite wisdom, created a 
> fixed purpose counter for which there is no equivalent in the 
> general purpose events.
> 
> Our fixed purpose counter support is predicated on the 
> assumption that there is, and simply maps any event code to 
> also include the fixed purpose counter if appropriate.
> 
> There not being an event to map from has thus far avoided 
> exposing this third fixed purpose event.
> 
> The problem with remapping BUS_CYCLES is that BUS_CYCLES (now) 
> is something you can program on the {2,4,8} general purpose 
> counters, whereas this new thing can only ever be ran from the 
> 1 fixed purpose counter.

Okay - if we want/need 3 variants then i have no objections.

Thanks,

	Ingo

Re: [PATCH 2/4] perf_event: add PERF_COUNT_HW_REF_CPU_CYCLES generic PMU event

[Stephane Eranian]

On Sun, Dec 11, 2011 at 4:55 AM, Peter Zijlstra <peterz@infradead.org> wrote:
> On Sun, 2011-12-11 at 09:01 +0100, Ingo Molnar wrote:
>> > +     PERF_COUNT_HW_REF_CPU_CYCLES            = 9,
>>
>> Btw., that was what 'bus cycles' tried to do a long time ago:
>> the constant, non-variable baseline heartbeat of the system.
>
> This isn't about that. Its about exposing the third fixed purpose
> counter. Intel, in their infinite wisdom, created a fixed purpose
> counter for which there is no equivalent in the general purpose events.
>
Peter is correct.

> Our fixed purpose counter support is predicated on the assumption that
> there is, and simply maps any event code to also include the fixed
> purpose counter if appropriate.
>
True.

> There not being an event to map from has thus far avoided exposing this
> third fixed purpose event.
>
> The problem with remapping BUS_CYCLES is that BUS_CYCLES (now) is
> something you can program on the {2,4,8} general purpose counters,
> whereas this new thing can only ever be ran from the 1 fixed purpose
> counter.
>
Fixed counter event do NOT have encodings. By constructions, this is
not needed. So far, perf_events was able to access 2 of the 3 fixed counter
events ONLY because they could ALSO be measured on generic counters.
In fact, the event scheduling algorithm as it stood until the AMD changes, put
those events on generic counters first, then fixed counters if needed.
But fixed counter 2 (counting unhalted_ref_cycles) is different. It cannot be
measured on generic counters.

BUS_CYCLES maps to an encoding for generic counters and it does count
clock ticks but not at the same rate as unhalted_reference_cycles (i.e., fixed
counter 2). In general bus_cycles counts at about 266Mhz  but could be higher
on some systems.
$ perf stat -e bus-cycles noploop 1
noploop for 1 seconds
 Performance counter stats for 'noploop 1':
         266062586 bus-cycles

Although there is a fixed ratio between that bus_cycles
(cpu_clk_unhalted:ref_p or bus)
and unhalted_reference_cycles, getting to it may not be easy. And then, if
you knew it, it could be kind of ugly to special case this event to adjust it
to count core ref cycles.

The patch chooses an encoding for the event, which means we can now name it.
The kernel then knows about that event (mapping table) and can avoid expanding
its list of supported counters to the generic counters.

I think expanding the list of generic HW events with this new one is
the simplest
way to make it available to tools. Users of raw events (like me) can also
use it via the raw encoding.

Re: [PATCH 2/4] perf_event: add PERF_COUNT_HW_REF_CPU_CYCLES generic PMU event

[Peter Zijlstra]

On Sun, 2011-12-11 at 00:28 +0100, Stephane Eranian wrote:
> This event counts the number of reference core cpu cycles.
> Reference means that the event increments at a constant rate which
> is not subject to core CPU frequency adjustments. The event may
> not count when the processor is in halted (low power) state.
> As such, it may not be equivalent to wall clock time. However,
> when the processor is not halted state, the event keeps
> a constant correlation with wall clock time.
> 
> Signed-off-by: Stephane Eranian <eranian@google.com>
> ---
>  include/linux/perf_event.h |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
> index 564769c..0885561 100644
> --- a/include/linux/perf_event.h
> +++ b/include/linux/perf_event.h
> @@ -54,6 +54,7 @@ enum perf_hw_id {
>  	PERF_COUNT_HW_BUS_CYCLES		= 6,
>  	PERF_COUNT_HW_STALLED_CYCLES_FRONTEND	= 7,
>  	PERF_COUNT_HW_STALLED_CYCLES_BACKEND	= 8,
> +	PERF_COUNT_HW_REF_CPU_CYCLES		= 9,
>  
>  	PERF_COUNT_HW_MAX,			/* non-ABI */
>  };

Does it make sense to add this to the 'generic' events? Are other archs
going to use this?

That is, I already queued patch 1, I'm just wondering if the generic bit
makes sense, Even BUS_CYCLES seems to be a questionable 'generic' event,
but that's history and we can't fix it.

Re: [PATCH 2/4] perf_event: add PERF_COUNT_HW_REF_CPU_CYCLES generic PMU event

[Ingo Molnar]

* Peter Zijlstra <peterz@infradead.org> wrote:

> On Sun, 2011-12-11 at 00:28 +0100, Stephane Eranian wrote:
> > This event counts the number of reference core cpu cycles.
> > Reference means that the event increments at a constant rate which
> > is not subject to core CPU frequency adjustments. The event may
> > not count when the processor is in halted (low power) state.
> > As such, it may not be equivalent to wall clock time. However,
> > when the processor is not halted state, the event keeps
> > a constant correlation with wall clock time.
> > 
> > Signed-off-by: Stephane Eranian <eranian@google.com>
> > ---
> >  include/linux/perf_event.h |    1 +
> >  1 files changed, 1 insertions(+), 0 deletions(-)
> > 
> > diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
> > index 564769c..0885561 100644
> > --- a/include/linux/perf_event.h
> > +++ b/include/linux/perf_event.h
> > @@ -54,6 +54,7 @@ enum perf_hw_id {
> >  	PERF_COUNT_HW_BUS_CYCLES		= 6,
> >  	PERF_COUNT_HW_STALLED_CYCLES_FRONTEND	= 7,
> >  	PERF_COUNT_HW_STALLED_CYCLES_BACKEND	= 8,
> > +	PERF_COUNT_HW_REF_CPU_CYCLES		= 9,
> >  
> >  	PERF_COUNT_HW_MAX,			/* non-ABI */
> >  };
> 
> Does it make sense to add this to the 'generic' events? Are 
> other archs going to use this?
> 
> That is, I already queued patch 1, I'm just wondering if the 
> generic bit makes sense, Even BUS_CYCLES seems to be a 
> questionable 'generic' event, but that's history and we can't 
> fix it.

If we named it in a generic way, with a generic, 
platform-independent meaning behind it, then it shouldn't be a 
problem. This is why i suggested naming it 'constant CPU cycles' 
- or 'constant freq cycles' or a variant of that.

Thanks,

	Ingo

Re: [PATCH 2/4] perf_event: add PERF_COUNT_HW_REF_CPU_CYCLES generic PMU event

[Stephane Eranian]

On Mon, Dec 12, 2011 at 9:32 AM, Ingo Molnar <mingo@elte.hu> wrote:
>
> * Peter Zijlstra <peterz@infradead.org> wrote:
>
>> On Sun, 2011-12-11 at 00:28 +0100, Stephane Eranian wrote:
>> > This event counts the number of reference core cpu cycles.
>> > Reference means that the event increments at a constant rate which
>> > is not subject to core CPU frequency adjustments. The event may
>> > not count when the processor is in halted (low power) state.
>> > As such, it may not be equivalent to wall clock time. However,
>> > when the processor is not halted state, the event keeps
>> > a constant correlation with wall clock time.
>> >
>> > Signed-off-by: Stephane Eranian <eranian@google.com>
>> > ---
>> >  include/linux/perf_event.h |    1 +
>> >  1 files changed, 1 insertions(+), 0 deletions(-)
>> >
>> > diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
>> > index 564769c..0885561 100644
>> > --- a/include/linux/perf_event.h
>> > +++ b/include/linux/perf_event.h
>> > @@ -54,6 +54,7 @@ enum perf_hw_id {
>> >     PERF_COUNT_HW_BUS_CYCLES                = 6,
>> >     PERF_COUNT_HW_STALLED_CYCLES_FRONTEND   = 7,
>> >     PERF_COUNT_HW_STALLED_CYCLES_BACKEND    = 8,
>> > +   PERF_COUNT_HW_REF_CPU_CYCLES            = 9,
>> >
>> >     PERF_COUNT_HW_MAX,                      /* non-ABI */
>> >  };
>>
>> Does it make sense to add this to the 'generic' events? Are
>> other archs going to use this?
>>
>> That is, I already queued patch 1, I'm just wondering if the
>> generic bit makes sense, Even BUS_CYCLES seems to be a
>> questionable 'generic' event, but that's history and we can't
>> fix it.
>
> If we named it in a generic way, with a generic,
> platform-independent meaning behind it, then it shouldn't be a
> problem. This is why i suggested naming it 'constant CPU cycles'
> - or 'constant freq cycles' or a variant of that.
>
Isn't CPU_REF_CYCLES good enough?
Should we speel out ref completely to 'REFERENCE'.
In the changelog, I gave a generic definition of what it is supposed to
measure. If most platforms don't have such events, then that's fine too.

Re: [PATCH 2/4] perf_event: add PERF_COUNT_HW_REF_CPU_CYCLES generic PMU event

[Peter Zijlstra]

On Mon, 2011-12-12 at 22:45 -0800, Stephane Eranian wrote:

> Isn't CPU_REF_CYCLES good enough?

I was just asking.. someone needs to ;-)

Took the remaining patches as well, thanks!

Re: [PATCH 2/4] perf_event: add PERF_COUNT_HW_REF_CPU_CYCLES generic PMU event

[Stephane Eranian]

On Tue, Dec 13, 2011 at 2:02 AM, Peter Zijlstra <peterz@infradead.org> wrote:
> On Mon, 2011-12-12 at 22:45 -0800, Stephane Eranian wrote:
>
>> Isn't CPU_REF_CYCLES good enough?
>
> I was just asking.. someone needs to ;-)
>
> Took the remaining patches as well, thanks!

Ok, thanks.

[tip:perf/core] perf events: Add PERF_COUNT_HW_REF_CPU_CYCLES generic PMU event

[tip-bot for Stephane Eranian]

Commit-ID:  c37e17497e01fc0f5d2d6feb5723b210b3ab8890
Gitweb:     http://git.kernel.org/tip/c37e17497e01fc0f5d2d6feb5723b210b3ab8890
Author:     Stephane Eranian <eranian@google.com>
AuthorDate: Sun, 11 Dec 2011 00:28:52 +0100
Committer:  Ingo Molnar <mingo@elte.hu>
CommitDate: Wed, 21 Dec 2011 10:26:37 +0100

perf events: Add PERF_COUNT_HW_REF_CPU_CYCLES generic PMU event

This event counts the number of reference core cpu cycles.
Reference means that the event increments at a constant rate which
is not subject to core CPU frequency adjustments. The event may
not count when the processor is in halted (low power) state.
As such, it may not be equivalent to wall clock time. However,
when the processor is not halted state, the event keeps
a constant correlation with wall clock time.

Signed-off-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/1323559734-3488-3-git-send-email-eranian@google.com
Signed-off-by: Ingo Molnar <mingo@elte.hu>
---
 include/linux/perf_event.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index 564769c..0885561 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -54,6 +54,7 @@ enum perf_hw_id {
 	PERF_COUNT_HW_BUS_CYCLES		= 6,
 	PERF_COUNT_HW_STALLED_CYCLES_FRONTEND	= 7,
 	PERF_COUNT_HW_STALLED_CYCLES_BACKEND	= 8,
+	PERF_COUNT_HW_REF_CPU_CYCLES		= 9,
 
 	PERF_COUNT_HW_MAX,			/* non-ABI */
 };

[PATCH 3/4] perf_events: add Intel X86 mapping for PERF_COUNT_HW_REF_CPU_CYCLES

[Stephane Eranian]

Add event mapps for Intel X86 processors (with architected PMU v2 or later)
and AMD.

On AMD, there is frequency scaling but no Turbo. There is no core
cycle event not subject to frequency scaling, therefore we do not provide
a mapping.

Signed-off-by: Stephane Eranian <eranian@google.com>
---
 arch/x86/kernel/cpu/perf_event_intel.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 61f865f..cbfaaa2 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -28,6 +28,7 @@ static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
   [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= 0x00c4,
   [PERF_COUNT_HW_BRANCH_MISSES]		= 0x00c5,
   [PERF_COUNT_HW_BUS_CYCLES]		= 0x013c,
+  [PERF_COUNT_HW_REF_CPU_CYCLES]	= 0x0300, /* pseudo-encoding */
 };
 
 static struct event_constraint intel_core_event_constraints[] __read_mostly =
-- 
1.7.1

[tip:perf/core] perf events: Add Intel x86 mapping for PERF_COUNT_HW_REF_CPU_CYCLES

[tip-bot for Stephane Eranian]

Commit-ID:  9c1497ea591b25d491f8e795f90a1405100b75ef
Gitweb:     http://git.kernel.org/tip/9c1497ea591b25d491f8e795f90a1405100b75ef
Author:     Stephane Eranian <eranian@google.com>
AuthorDate: Sun, 11 Dec 2011 00:28:53 +0100
Committer:  Ingo Molnar <mingo@elte.hu>
CommitDate: Wed, 21 Dec 2011 10:26:39 +0100

perf events: Add Intel x86 mapping for PERF_COUNT_HW_REF_CPU_CYCLES

Add event maps for Intel x86 processors (with architected PMU v2 or later).

On AMD, there is frequency scaling but no Turbo. There is no core
cycle event not subject to frequency scaling, therefore we do not
provide a mapping.

Signed-off-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/1323559734-3488-4-git-send-email-eranian@google.com
Signed-off-by: Ingo Molnar <mingo@elte.hu>
---
 arch/x86/kernel/cpu/perf_event_intel.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 61f865f..cbfaaa2 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -28,6 +28,7 @@ static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
   [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= 0x00c4,
   [PERF_COUNT_HW_BRANCH_MISSES]		= 0x00c5,
   [PERF_COUNT_HW_BUS_CYCLES]		= 0x013c,
+  [PERF_COUNT_HW_REF_CPU_CYCLES]	= 0x0300, /* pseudo-encoding */
 };
 
 static struct event_constraint intel_core_event_constraints[] __read_mostly =

[PATCH 4/4] perf: add support for PERF_HW_COUNT_REF_CPU_CYCLES

[Stephane Eranian]

add new generic hw event: ref-cycles
maps to PERF_HW_COUNT_REF_CPUCYCLES.

$ perf stat -e ref-cycles ls

Signed-off-by: Stephane Eranian <eranian@google.com>
---
 tools/perf/util/parse-events.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c
index 586ab3f..531c283 100644
--- a/tools/perf/util/parse-events.c
+++ b/tools/perf/util/parse-events.c
@@ -38,6 +38,7 @@ static struct event_symbol event_symbols[] = {
   { CHW(BRANCH_INSTRUCTIONS),		"branch-instructions",		"branches"		},
   { CHW(BRANCH_MISSES),			"branch-misses",		""			},
   { CHW(BUS_CYCLES),			"bus-cycles",			""			},
+  { CHW(REF_CPU_CYCLES),		"ref-cycles",			""			},
 
   { CSW(CPU_CLOCK),			"cpu-clock",			""			},
   { CSW(TASK_CLOCK),			"task-clock",			""			},
@@ -68,6 +69,7 @@ static const char *hw_event_names[PERF_COUNT_HW_MAX] = {
 	"bus-cycles",
 	"stalled-cycles-frontend",
 	"stalled-cycles-backend",
+	"ref-cycles",
 };
 
 static const char *sw_event_names[PERF_COUNT_SW_MAX] = {
-- 
1.7.1

[tip:perf/core] perf: Add support for PERF_HW_COUNT_REF_CPU_CYCLES

[tip-bot for Stephane Eranian]

Commit-ID:  f1ac18af219835fd5b8e19c14d2dd75c55f78737
Gitweb:     http://git.kernel.org/tip/f1ac18af219835fd5b8e19c14d2dd75c55f78737
Author:     Stephane Eranian <eranian@google.com>
AuthorDate: Sun, 11 Dec 2011 00:28:54 +0100
Committer:  Ingo Molnar <mingo@elte.hu>
CommitDate: Wed, 21 Dec 2011 10:26:41 +0100

perf: Add support for PERF_HW_COUNT_REF_CPU_CYCLES

Add new generic hw event: ref-cycles, which maps to
PERF_HW_COUNT_REF_CPUCYCLES:

 $ perf stat -e ref-cycles ls

Signed-off-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/1323559734-3488-5-git-send-email-eranian@google.com
Signed-off-by: Ingo Molnar <mingo@elte.hu>
---
 tools/perf/util/parse-events.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c
index 586ab3f..531c283 100644
--- a/tools/perf/util/parse-events.c
+++ b/tools/perf/util/parse-events.c
@@ -38,6 +38,7 @@ static struct event_symbol event_symbols[] = {
   { CHW(BRANCH_INSTRUCTIONS),		"branch-instructions",		"branches"		},
   { CHW(BRANCH_MISSES),			"branch-misses",		""			},
   { CHW(BUS_CYCLES),			"bus-cycles",			""			},
+  { CHW(REF_CPU_CYCLES),		"ref-cycles",			""			},
 
   { CSW(CPU_CLOCK),			"cpu-clock",			""			},
   { CSW(TASK_CLOCK),			"task-clock",			""			},
@@ -68,6 +69,7 @@ static const char *hw_event_names[PERF_COUNT_HW_MAX] = {
 	"bus-cycles",
 	"stalled-cycles-frontend",
 	"stalled-cycles-backend",
+	"ref-cycles",
 };
 
 static const char *sw_event_names[PERF_COUNT_SW_MAX] = {