From: Peter Zijlstra <a.p.zijlstra@chello.nl>
To: Ingo Molnar <mingo@elte.hu>
Cc: "Lénaïc Huard" <lenaic@lhuard.fr.eu.org>,
"Paul Mackerras" <paulus@samba.org>,
"Arnaldo Carvalho de Melo" <acme@ghostprotocols.net>,
linux-kernel@vger.kernel.org
Subject: Re: Shift by one instruction in the perf annotate output
Date: Fri, 27 Jan 2012 11:49:24 +0100 [thread overview]
Message-ID: <1327661364.2446.159.camel@twins> (raw)
In-Reply-To: <20120127104442.GB31782@elte.hu>
On Fri, 2012-01-27 at 11:44 +0100, Ingo Molnar wrote:
> * Peter Zijlstra <a.p.zijlstra@chello.nl> wrote:
>
> > On Fri, 2012-01-27 at 11:27 +0100, Ingo Molnar wrote:
> >
> > > On Core2 CPUs there's PEBS so 'p' will work, but there's no
> > > LBR so the IP-rewinding does not work.
> >
> > Not on his thing.. PEBS is a trainwreck on model 15.
>
> ok - i have a model 23, there it works:
>
> [ 0.044260] CPU0: Intel(R) Core(TM)2 Duo CPU T9600 @ 2.80GHz stepping 06
> [ 0.044996] Performance Events: PEBS fmt0+, Core2 events, Intel PMU driver.
Right, only model 15 the very first core2 chips were badly broken, they
fixed it in the shrink (model 22,23,29).
And as you know, something got screwy in SNB (model 42) so that's got
PEBS fully disabled until further notice as well.
prev parent reply other threads:[~2012-01-27 10:49 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-01-26 23:01 Shift by one instruction in the perf annotate output Lénaïc Huard
2012-01-27 6:50 ` Mike Galbraith
2012-01-27 8:15 ` Peter Zijlstra
2012-01-27 10:27 ` Ingo Molnar
2012-01-27 10:40 ` Peter Zijlstra
2012-01-27 10:44 ` Ingo Molnar
2012-01-27 10:49 ` Peter Zijlstra [this message]
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