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From: "Alex,Shi" <alex.shi@intel.com>
To: tglx@linutronix.de, hpa@zytor.com, mingo@redhat.com
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	x86@kernel.org, asit.k.mallick@intel.com
Subject: change last level cache alignment on x86?
Date: Thu, 01 Mar 2012 16:33:36 +0800	[thread overview]
Message-ID: <1330590816.21053.1336.camel@debian> (raw)

Currently last level defined in kernel is still 128 bytes, but actually
I checked intel's core2, NHM, SNB, atom, serial platforms, all of them
are using 64 bytes. 
I did not get detailed info on AMD platforms. Guess someone like to give
the info here. So, Is if it possible to do the similar following changes
to use 64 byte cache alignment in kernel?

===
diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
index 3c57033..f342a5a 100644
--- a/arch/x86/Kconfig.cpu
+++ b/arch/x86/Kconfig.cpu
@@ -303,7 +303,7 @@ config X86_GENERIC
 config X86_INTERNODE_CACHE_SHIFT
 	int
 	default "12" if X86_VSMP
-	default "7" if NUMA
+	default "7" if NUMA && (MPENTIUM4)
 	default X86_L1_CACHE_SHIFT
 
 config X86_CMPXCHG



             reply	other threads:[~2012-03-01  8:34 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-03-01  8:33 Alex,Shi [this message]
2012-03-02  7:30 ` change last level cache alignment on x86? Alex Shi
2012-03-02  8:12   ` Ingo Molnar
2012-03-02 14:42     ` Alex Shi
2012-03-02 15:25       ` Ingo Molnar
2012-03-03 11:30         ` Alex Shi

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