From: Chris Wilson <chris@chris-wilson.co.uk>
To: Daniel Kurtz <djkurtz@chromium.org>
Cc: Daniel Vetter <daniel@ffwll.ch>,
Keith Packard <keithp@keithp.com>,
David Airlie <airlied@linux.ie>,
dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
Benson Leung <bleung@chromium.org>,
Yufeng Shen <miletus@chromium.org>
Subject: Re: [PATCH 14/14 v5] drm/i915/intel_i2c: remove POSTING_READ() from gmbus transfers
Date: Wed, 28 Mar 2012 15:30:13 +0100 [thread overview]
Message-ID: <1332945027_128384@CP5-2952> (raw)
In-Reply-To: <CAGS+omAJaEaGUNY6V=sGNOWHxhb3YRv2mPcuUwQV99ksvsNP4Q@mail.gmail.com>
On Wed, 28 Mar 2012 21:21:42 +0800, Daniel Kurtz <djkurtz@chromium.org> wrote:
> On Wed, Mar 28, 2012 at 9:05 PM, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> > We do need the write flush here (and set_data) as the next action is a
> > udelay loop which is not per-se a mb.
>
> Now I am confused. I915_WRITE_NOTRACE() calls writel(), which has an
> explicit mb(); Why do you need another mb?
Nominally writel isn't a memory barrier. I see that x86 does include mb
in its writel define. However, if memory serves, that is only a write
barrier to memory (equivalent of mfence), and not a PCI write flush/barrier
for which we need to an explicit PCI read.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
next prev parent reply other threads:[~2012-03-28 14:30 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-03-28 12:51 [PATCH 00/14 v5] fix gmbus writes and related issues Daniel Kurtz
2012-03-28 12:51 ` [PATCH 01/14 v5] drm/i915/intel_i2c: refactor gmbus_xfer Daniel Kurtz
2012-03-28 12:51 ` [PATCH 02/14 v5] drm/i915/intel_i2c: cleanup error messages and comments Daniel Kurtz
2012-03-28 12:51 ` [PATCH 03/14 v5] drm/i915/intel_i2c: assign HDMI port D to pin pair 6 Daniel Kurtz
2012-03-28 12:51 ` [PATCH 04/14 v5] drm/i915/intel_i2c: use i2c pre/post_xfer functions to setup gpio xfers Daniel Kurtz
2012-03-28 12:51 ` [PATCH 05/14 v5] drm/i915/intel_i2c: refactor using intel_gmbus_get_adapter Daniel Kurtz
2012-03-28 12:51 ` [PATCH 06/14 v5] drm/i915/intel_i2c: gmbus disabled and reserved ports are invalid Daniel Kurtz
2012-03-28 12:51 ` [PATCH 07/14 v5] drm/i915/intel_i2c: allocate gmbus array as part of drm_i915_private Daniel Kurtz
2012-03-28 12:51 ` [PATCH 08/14 v5] drm/i915/intel_i2c: handle zero-length writes Daniel Kurtz
2012-03-28 12:51 ` [PATCH 09/14 v5] drm/i915/intel_i2c: use double-buffered writes Daniel Kurtz
2012-03-28 12:51 ` [PATCH 10/14 v5] drm/i915/intel_i2c: always wait for IDLE before clearing NAK Daniel Kurtz
2012-03-28 12:51 ` [PATCH 11/14 v5] drm/i915/intel_i2c: use WAIT cycle, not STOP Daniel Kurtz
2012-03-28 12:51 ` [PATCH 12/14 v5] drm/i915/intel_i2c: use INDEX cycles for i2c read transactions Daniel Kurtz
2012-03-28 12:51 ` [PATCH 13/14 v5] drm/i915/intel_i2c: reuse GMBUS2 value read in polling loop Daniel Kurtz
2012-03-28 12:51 ` [PATCH 14/14 v5] drm/i915/intel_i2c: remove POSTING_READ() from gmbus transfers Daniel Kurtz
2012-03-28 13:05 ` Chris Wilson
2012-03-28 13:21 ` Daniel Kurtz
2012-03-28 14:30 ` Chris Wilson [this message]
2012-03-28 14:46 ` Daniel Vetter
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