From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: Milton Miller <miltonm@bga.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
Yinghai Lu <yinghai@kernel.org>,
Jesse Barnes <jbarnes@virtuousgeek.org>,
Tony Luck <tony.luck@intel.com>,
Dominik Brodowski <linux@dominikbrodowski.net>,
Andrew Morton <akpm@linux-foundation.org>,
Linus Torvalds <torvalds@linux-foundation.org>,
Greg Kroah-Hartmann <greg@kroah.com>,
lkml <linux-kernel@vger.kernel.org>,
linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH 08/18] PCI, powerpc: Register busn_res for root buses
Date: Tue, 03 Apr 2012 07:22:47 +1000 [thread overview]
Message-ID: <1333401767.30734.58.camel@pasglop> (raw)
In-Reply-To: <powerpc-pci-domains-by-busnumber-resend@mdm.bga.com>
On Mon, 2012-04-02 at 05:19 -0500, Milton Miller wrote:
>
> In the POWER3 era we had several boxes that split the pci bus number
> space across domains and RTAS used the bus number to find the correct
> PHB. This contineed to the first RS64 boxes. By S80 and RS64-III
> it was obvious that we didn't have enough numbers to continue this
> ilusion and we added the presently used RTAS calls that take the pci
> domain as well as bus, device, and function numbers.
>
> The bus numbers split across pci domains started with the F50
> F50 chrp 32 bit platforms.
Ok, so old CHRPs would have a split as well...
I think the best is to honor the bus-range property of the PHB as min &
max values, and if we feel a need to allow the kernel to assign busses
beyond that, we can always quirk the appropriate platform code.
Cheers,
Ben.
next prev parent reply other threads:[~2012-04-02 21:23 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-02-28 2:09 [PATCH -v8 0/18] PCI: allocate pci bus num range for unassigned bridge busn Yinghai Lu
2012-02-28 2:09 ` [PATCH 01/18] x86, PCI: Merge pcibios_scan_root and pci_scan_bus_on_node Yinghai Lu
2012-02-28 2:09 ` [PATCH 02/18] PCI: Add busn_res into struct pci_bus Yinghai Lu
2012-02-28 2:09 ` [PATCH 03/18] PCI: Add busn_res operation functions Yinghai Lu
2012-02-28 2:09 ` [PATCH 04/18] PCI: Add busn_res tracking in core Yinghai Lu
2012-02-28 2:09 ` [PATCH 05/18] PCI, x86: Register busn_res for root buses Yinghai Lu
2012-02-28 2:09 ` [PATCH 06/18] PCI, ia64: " Yinghai Lu
2012-02-28 2:09 ` [PATCH 07/18] PCI, sparc: " Yinghai Lu
2012-02-28 2:09 ` [PATCH 08/18] PCI, powerpc: " Yinghai Lu
2012-02-28 5:36 ` Bjorn Helgaas
2012-02-28 8:54 ` Benjamin Herrenschmidt
2012-02-28 23:31 ` Bjorn Helgaas
2012-02-28 23:41 ` Benjamin Herrenschmidt
2012-04-02 10:19 ` Milton Miller
2012-04-02 21:22 ` Benjamin Herrenschmidt [this message]
2012-02-28 2:10 ` [PATCH 09/18] PCI, parisc: " Yinghai Lu
2012-02-28 2:10 ` [PATCH 10/18] PCI: Add pci_bus_extend/shrink_top() Yinghai Lu
2012-02-28 2:10 ` [PATCH 11/18] PCI: Probe safe range that we can use for unassigned bridge Yinghai Lu
2012-02-28 2:10 ` [PATCH 12/18] PCI: Strict checking of valid range for bridge Yinghai Lu
2012-02-28 2:10 ` [PATCH 13/18] PCI: Allocate bus range instead of use max blindly Yinghai Lu
2012-02-28 2:10 ` [PATCH 14/18] PCI: kill pci_fixup_parent_subordinate_busnr() Yinghai Lu
2012-02-28 2:10 ` [PATCH 15/18] PCI: Seperate child bus scanning to two passes overall Yinghai Lu
2012-02-28 2:10 ` [PATCH 16/18] pcmcia: remove workaround for fixing pci parent bus subordinate Yinghai Lu
2012-02-28 2:10 ` [PATCH 17/18] PCI: Double checking setting for bus register and bus struct Yinghai Lu
2012-02-28 2:10 ` [PATCH 18/18] PCI, pciehp: Remove not needed bus number range checking Yinghai Lu
2012-02-28 10:03 ` [PATCH -v8 0/23] PCI: allocate pci bus num range for unassigned bridge busn Yinghai Lu
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