From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932561Ab2DSWJu (ORCPT ); Thu, 19 Apr 2012 18:09:50 -0400 Received: from mail-wi0-f172.google.com ([209.85.212.172]:39358 "EHLO mail-wi0-f172.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932375Ab2DSWJt (ORCPT ); Thu, 19 Apr 2012 18:09:49 -0400 From: Ido Yariv To: linux-kernel@vger.kernel.org, Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" Cc: Shai Fultheim , Ido Yariv Subject: [PATCH RESEND] x86: cache_info: Fix setup of l2/l3 ids Date: Fri, 20 Apr 2012 01:09:11 +0300 Message-Id: <1334873351-31142-1-git-send-email-ido@wizery.com> X-Mailer: git-send-email 1.7.7.6 In-Reply-To: <1333715894-25995-1-git-send-email-ido@wizery.com> References: <1333715894-25995-1-git-send-email-ido@wizery.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Shai Fultheim On some architectures (such as vSMP), it is possible to have CPUs with a different number of cores sharing the same cache. The current implementation implicitly assumes that all CPUs will have the same number of cores sharing caches, and as a result, different CPUs can end up with the same l2/l3 ids. Fix this by masking out the shared cache bits, instead of shifting the APICID. By doing so, it is guaranteed that the generated cache ids are always unique. Signed-off-by: Shai Fultheim [ido@wizery.com: rebased, simplified, and reworded the commit message] Signed-off-by: Ido Yariv --- arch/x86/kernel/cpu/intel_cacheinfo.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c index 73d08ed..caa6cb0 100644 --- a/arch/x86/kernel/cpu/intel_cacheinfo.c +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c @@ -615,14 +615,14 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c) new_l2 = this_leaf.size/1024; num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing; index_msb = get_count_order(num_threads_sharing); - l2_id = c->apicid >> index_msb; + l2_id = c->apicid & ~((1 << index_msb) - 1); break; case 3: new_l3 = this_leaf.size/1024; num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing; index_msb = get_count_order( num_threads_sharing); - l3_id = c->apicid >> index_msb; + l3_id = c->apicid & ~((1 << index_msb) - 1); break; default: break; -- 1.7.7.6