Re: [PATCH v3 4/7] x86/tlb: add tlb flush all factor for specific CPUs

[Peter Zijlstra <a.p.zijlstra@chello.nl>]

On Tue, 2012-05-08 at 22:03 +0800, Alex Shi wrote:
> +void intel_tlb_flushall_factor_set(struct cpuinfo_x86 *c)
> +{
> +       switch (c->x86_model) {
> +       case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
> +               tlb_flushall_factor = 0;
> +               break;

Why isn't this is the bottom list of core chips?

> +       case 26: /* 45 nm nehalem, "Bloomfield" */
> +       case 30: /* 45 nm nehalem, "Lynnfield" */
> +       case 37: /* 32 nm nehalem, "Clarkdale" */
> +       case 44: /* 32 nm nehalem, "Gulftown" */
> +       case 46: /* 45 nm nehalem-ex, "Beckton" */
> +               tlb_flushall_factor = 64;
> +               break;
> +       case 42: /* SandyBridge */
> +       case 45: /* SandyBridge, "Romely-EP" */
> +               tlb_flushall_factor = 32;
> +               break;
> +       case 28: /* Atom */
> +       case 47: /* 32 nm Xeon E7 */

This is a wsm-ex, right? Why isn't it listed with the other nehalems?

> +       case 14: /* 65 nm core solo/duo, "Yonah" */
> +       case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
> +       case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
> +       case 29: /* six-core 45 nm xeon "Dunnington" */

So never use invlpg for Atom/Core/Core2?

> +       default:
> +               tlb_flushall_factor = 0;
> +       }
> +}


> @@ -364,7 +363,8 @@ flush_all:
>                         act_entries = tlb_entries > mm->total_vm ?
>                                         mm->total_vm : tlb_entries;
>  
> +                       if ((end - start)/PAGE_SIZE >
> +                                       act_entries/tlb_flushall_factor) 

You're doing an actual full division, wouldn't a shift be better?