Re: [PATCH] perf, x86: Make cycles:p working on SNB

[Peter Zijlstra <a.p.zijlstra@chello.nl>]

On Thu, 2012-05-24 at 09:41 +0200, Stephane Eranian wrote:
> So should we mark that
> > as bad as well?
> >
> I never could but was told it was there too.
> 
> > Also, do you happen to know if/when a u-code update would appear?
> >
> I am hoping Intel will release the ucode update very soon now. I will
> post a patch
> to re-enable PEBS on model 42 when that happens.

OK, so how about I queue the below and if the u-code updates gets
released before this hits Linus' tree we'll make it all go away ;-)

---
Subject: perf,x86: Mark PEBS as broken on SNB-EP as well

As per information from Intel.

Cc: Stephane Eranian <eranian@google.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
---
 arch/x86/kernel/cpu/perf_event_intel.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 166546e..6c8e400 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -1840,8 +1840,8 @@ __init int intel_pmu_init(void)
 		break;
 
 	case 42: /* SandyBridge */
-		x86_add_quirk(intel_sandybridge_quirk);
 	case 45: /* SandyBridge, "Romely-EP" */
+		x86_add_quirk(intel_sandybridge_quirk);
 		memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
 		       sizeof(hw_cache_event_ids));