From: Peter Zijlstra <peterz@infradead.org>
To: David Ahern <dsahern@gmail.com>
Cc: Stephane Eranian <eranian@google.com>,
LKML <linux-kernel@vger.kernel.org>,
Gleb Natapov <gleb@redhat.com>, Avi Kivity <avi@redhat.com>
Subject: Re: perf, x86: only do lbr init if bts is available
Date: Thu, 24 May 2012 19:21:09 +0200 [thread overview]
Message-ID: <1337880069.9698.70.camel@twins> (raw)
In-Reply-To: <1337879916.9698.69.camel@twins>
On Thu, 2012-05-24 at 19:18 +0200, Peter Zijlstra wrote:
> Right, as Stephane already noted, LBR is not an CPUID enumerated
> feature, hence the only thing you can do is go by model. So if you set
> qemu -cpu host but fail to implement all the architectural MSRs that go
> with that model you get to keep the pieces.
s/architectural//
They're called Model-Specific-Registers for a reason ;-)
prev parent reply other threads:[~2012-05-24 17:21 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-05-24 16:19 perf, x86: only do lbr init if bts is available David Ahern
2012-05-24 16:35 ` Stephane Eranian
2012-05-24 16:41 ` David Ahern
2012-05-24 17:07 ` David Ahern
2012-05-24 17:11 ` Stephane Eranian
2012-05-25 22:49 ` Andi Kleen
2012-05-24 17:18 ` Peter Zijlstra
2012-05-24 17:21 ` Peter Zijlstra [this message]
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