From: Peter Zijlstra <a.p.zijlstra@chello.nl>
To: Stephane Eranian <eranian@google.com>
Cc: Andi Kleen <ak@linux.intel.com>, Andi Kleen <andi@firstfloor.org>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 5/5] perf, x86: Prefer RDPMC over RDMSR for reading counters
Date: Wed, 06 Jun 2012 16:38:44 +0200 [thread overview]
Message-ID: <1338993524.2749.122.camel@twins> (raw)
In-Reply-To: <CABPqkBQ7xwK+BjYainpxXV+D_KjMgH0KFVhYK9w89TxqQOF_MQ@mail.gmail.com>
On Wed, 2012-06-06 at 16:33 +0200, Stephane Eranian wrote:
> Yes, his patch did but somehow I don't see this code in tip-x86.
> The thing that I would worry about between rdmsrl() and rdpmc()
> is what happens to the upper bits. rdpmc() returns bits [N-1:0] of
> the N-bit counters. N is 48 (or 40) nowadays. When you read 64 bit
> worth, what do you get in bits [63:N]? are those sign-extended or
> zero-extended. Is that the same behavior across all Intel and AMD
> processors? With perf_events, I think the (N-1)th bit is always set.
>
Queued his patch after I saw Andi's trainwreck -- had totally forgotten
about it :/
For the kernel it doesn't matter, we manually sign-extend for however
many bits the counter has.
next prev parent reply other threads:[~2012-06-06 14:38 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-06-06 0:56 [PATCH 1/5] perf, x86: Don't assume the alternative cycles encoding is architectural Andi Kleen
2012-06-06 0:56 ` [PATCH 2/5] perf, x86: Don't assume there can be only 4 PEBS events Andi Kleen
2012-06-06 15:00 ` Peter Zijlstra
2012-06-06 16:10 ` Andi Kleen
2012-06-06 17:25 ` Peter Zijlstra
2012-06-06 16:17 ` [tip:perf/core] perf/x86: Don' t " tip-bot for Andi Kleen
2012-06-06 0:56 ` [PATCH 3/5] perf, x86: Check LBR format capability Andi Kleen
2012-06-06 4:29 ` Andi Kleen
2012-06-06 10:40 ` Peter Zijlstra
2012-06-06 14:14 ` Andi Kleen
2012-06-06 14:22 ` Peter Zijlstra
2012-06-06 14:37 ` Andi Kleen
2012-06-06 0:56 ` [PATCH 4/5] x86: Add rdpmcl() Andi Kleen
2012-06-06 16:16 ` [tip:perf/core] " tip-bot for Andi Kleen
2012-06-06 0:56 ` [PATCH 5/5] perf, x86: Prefer RDPMC over RDMSR for reading counters Andi Kleen
2012-06-06 10:46 ` Peter Zijlstra
2012-06-06 14:16 ` Andi Kleen
2012-06-06 14:21 ` Peter Zijlstra
2012-06-06 14:33 ` Stephane Eranian
2012-06-06 14:38 ` Peter Zijlstra [this message]
2012-06-06 14:41 ` Andi Kleen
2012-06-06 14:45 ` Peter Zijlstra
2012-06-06 10:39 ` [PATCH 1/5] perf, x86: Don't assume the alternative cycles encoding is architectural Peter Zijlstra
2012-06-06 14:12 ` Andi Kleen
2012-06-06 14:14 ` Peter Zijlstra
2012-06-06 14:23 ` Andi Kleen
2012-06-06 14:28 ` Peter Zijlstra
2012-06-06 14:35 ` Andi Kleen
2012-06-06 14:42 ` Peter Zijlstra
2012-06-06 14:49 ` Andi Kleen
2012-06-06 14:53 ` Peter Zijlstra
2012-06-06 16:08 ` Andi Kleen
2012-06-06 17:10 ` Peter Zijlstra
2012-06-06 17:48 ` Andi Kleen
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