Re: [PATCH 2/5] perf, x86: Don't assume there can be only 4 PEBS events

Andi Kleen
2012-06-06T16:10:46Z

On Wed, Jun 06, 2012 at 05:00:03PM +0200, Peter Zijlstra wrote:
> On Tue, 2012-06-05 at 17:56 -0700, Andi Kleen wrote:
> > On Sandy Bridge in non HT mode there are 8 counters available. Since every
> > counter can write a PEBS record assuming there are 4 max is incorrect. Use
> > the reported counter number -- with an upper limit for a static array -- instead.
>
>
> While I queued this patch, its effectively a NOP since all SNB PEBS
> constraints are still on 4 counters.

Yes need to update the constraints too. I think Stephane was looking at that.
Perhaps two sets depending on the counters in CPUID?

FWIW I saw the warn on triggering.

-Andi
--
ak@linux.intel.com -- Speaking for myself only.