Re: [PATCH 3/5] perf, x86: Check LBR format capability

Andi Kleen
2012-06-06T04:29:17Z

Andi Kleen <andi@firstfloor.org> writes:

> From: Andi Kleen <ak@linux.intel.com>
>
> Double check the CPU has a LBR format we support before using it.

Sorry this was an outdated version with a missing return. Here's
the correct one.

---

From: Andi Kleen <ak@linux.intel.com>
Date: Tue, 29 May 2012 20:00:05 -0700
Subject: [PATCH] perf, x86: Check LBR format capability

Double check the CPU has a LBR format we support before using it.

Also I made the init functions __init while I was on it.

Signed-off-by: Andi Kleen <ak@linux.intel.com>

diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
index 520b426..753eed9 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
@@ -12,6 +12,7 @@ enum {
LBR_FORMAT_LIP = 0x01,
LBR_FORMAT_EIP = 0x02,
LBR_FORMAT_EIP_FLAGS = 0x03,
+ LBR_FORMAT_MAX = LBR_FORMAT_EIP_FLAGS
};

/*
@@ -622,9 +623,21 @@ static const int snb_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX] = {
[PERF_SAMPLE_BRANCH_IND_CALL] = LBR_IND_CALL,
};

+static bool lbr_common_init(void)
+{
+ if (x86_pmu.intel_cap.lbr_format > LBR_FORMAT_MAX) {
+ pr_cont("LBR has unknown format, ");
+ return false;
+ }
+ return true;
+}
+
/* core */
-void intel_pmu_lbr_init_core(void)
+__init void intel_pmu_lbr_init_core(void)
{
+ if (!lbr_common_init())
+ return;
+
x86_pmu.lbr_nr = 4;
x86_pmu.lbr_tos = MSR_LBR_TOS;
x86_pmu.lbr_from = MSR_LBR_CORE_FROM;
@@ -638,8 +651,11 @@ void intel_pmu_lbr_init_core(void)
}

/* nehalem/westmere */
-void intel_pmu_lbr_init_nhm(void)
+__init void intel_pmu_lbr_init_nhm(void)
{
+ if (!lbr_common_init())
+ return;
+
x86_pmu.lbr_nr = 16;
x86_pmu.lbr_tos = MSR_LBR_TOS;
x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
@@ -659,8 +675,11 @@ void intel_pmu_lbr_init_nhm(void)
}

/* sandy bridge */
-void intel_pmu_lbr_init_snb(void)
+__init void intel_pmu_lbr_init_snb(void)
{
+ if (!lbr_common_init())
+ return;
+
x86_pmu.lbr_nr = 16;
x86_pmu.lbr_tos = MSR_LBR_TOS;
x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
@@ -679,7 +698,7 @@ void intel_pmu_lbr_init_snb(void)
}

/* atom */
-void intel_pmu_lbr_init_atom(void)
+__init void intel_pmu_lbr_init_atom(void)
{
/*
* only models starting at stepping 10 seems
@@ -690,6 +709,8 @@ void intel_pmu_lbr_init_atom(void)
pr_cont("LBR disabled due to erratum");
return;
}
+ if (!lbr_common_init())
+ return;

x86_pmu.lbr_nr = 8;
x86_pmu.lbr_tos = MSR_LBR_TOS;

--
ak@linux.intel.com -- Speaking for myself only