[PATCH 2/7] dw_dmac: fill optional encoded parameters in register structure

Andy Shevchenko
2012-09-17T07:40:44Z

There is a block of the registers that are optional. However, if enabled they
contain useful information about the controller hardware configuration. We will
use this piece of data to autoconfigure the driver.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/dma/dw_dmac_regs.h | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)

diff --git a/drivers/dma/dw_dmac_regs.h b/drivers/dma/dw_dmac_regs.h
index f6d92d7..4633d39 100644
--- a/drivers/dma/dw_dmac_regs.h
+++ b/drivers/dma/dw_dmac_regs.h
@@ -82,9 +82,28 @@ struct dw_dma_regs {
DW_REG(ID);
DW_REG(TEST);

+ /* reserved */
+ DW_REG(__reserved0);
+ DW_REG(__reserved1);
+
/* optional encoded params, 0x3c8..0x3f7 */
+ u32 __reserved;
+
+ /* per-channel configuration registers */
+ u32 DWC_PARAMS[DW_DMA_MAX_NR_CHANNELS];
+ u32 MULTI_BLK_TYPE;
+ u32 MAX_BLK_SIZE;
+
+ /* top-level parameters */
+ u32 DW_PARAMS;
};

+#define dma_raw_readl(addr, name) \
+ readl((addr) + offsetof(struct dw_dma_regs, name))
+
+#define dma_raw_writel(addr, name, val) \
+ writel((val), (addr) + offsetof(struct dw_dma_regs, name))
+
/* Bitfields in CTL_LO */
#define DWC_CTLL_INT_EN (1 << 0) /* irqs enabled? */
#define DWC_CTLL_DST_WIDTH(n) ((n)<<1) /* bytes per element */
--
1.7.10.4